JAJSPW8 データシート | TI.com

JAJSPW8E march 2011 – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）

RGC|64
- MPQF125F

サーマルパッド・メカニカル・データ

RGC|64
- QFND123N

発注情報

7.12.3 ADS4242

At T_A = 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, maximum rated sampling frequency, sine wave input clock, 1.5-V_PP differential clock amplitude, 50% clock duty cycle, –1 dBFS differential analog input, High-Performance Mode disabled, 0-dB gain, DDR LVDS output interface, and 32k point FFT, unless otherwise noted.

Figure 7-48 FFT for 20-MHz Input Signal

Figure 7-50 FFT for 300-MHz Input Signal

Figure 7-52 FFT for Two-Tone Input Signal

Figure 7-54 SNR vs Input Frequency

Figure 7-56 SFDR vs Gain and Input Frequency

Figure 7-58 Performance vs Input Amplitude

Figure 7-60 Performance vs Input Common-Mode Voltage

Figure 7-62 SFDR vs Temperature and AVDD Supply

Figure 7-64 Performance vs DRVDD Supply Voltage

Figure 7-66 Performance vs Input Clock Amplitude

Figure 7-68 Integrated Nonlinearity

Figure 7-49 FFT for 170-MHz Input Signal

Figure 7-51 FFT for Two-Tone Input Signal

Figure 7-53 SFDR vs Input Frequency

Figure 7-55 SNR vs Input Frequency (CMOS)

Figure 7-57 SINAD vs Gain and Input Frequency

Figure 7-59 Performance vs Input Amplitude

Figure 7-61 Performance vs Input Common-Mode Voltage

Figure 7-63 SNR vs Temperature and AVDD Supply

Figure 7-65 Performance vs Input Clock Amplitude

Figure 7-67 Performance Across Input Clock Duty Cycle

Figure 7-69 Output Noise Histogram (With Inputs Shorted to VCM)