JAJSPW8E march   2011  – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions – LVDS Mode
    2.     Pin Functions – CMOS Mode
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 7.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes #GUID-C6C0701B-A11B-492F-BD6B-B774F5FE4665/SLAS6895399
    10. 7.10 Serial Interface Timing Characteristics #GUID-3852E7CE-C5B6-42F5-A56A-70AB1B981302/SBAS5097810
    11. 7.11 Reset Timing (Only When Serial Interface Is Used)
    12. 7.12 Typical Characteristics
      1. 7.12.1 ADS4246
      2. 7.12.2 ADS4245
      3. 7.12.3 ADS4242
      4. 7.12.4 ADS4226
      5. 7.12.5 ADS4225
      6. 7.12.6 ADS4222
      7. 7.12.7 General
      8. 7.12.8 Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Drive Circuit Requirements
        2. 8.3.1.2 Driving Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 Digital Functions
      4. 8.3.4 Gain for SFDR/SNR Trade-off
      5. 8.3.5 Offset Correction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down
        1. 8.4.1.1 Global Power-Down
        2. 8.4.1.2 Channel Standby
        3. 8.4.1.3 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 47
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
      7. 8.5.7 Digital Output Information
        1. 8.5.7.1 Output Interface
        2. 8.5.7.2 DDR LVDS Outputs
        3. 8.5.7.3 LVDS Buffer
        4. 8.5.7.4 Parallel CMOS Interface
        5. 8.5.7.5 CMOS Interface Power Dissipation
        6. 8.5.7.6 Multiplexed Mode of Operation
        7. 8.5.7.7 Output Data Format
    6. 8.6 Register Maps
      1. 8.6.1 64
      2. 8.6.2 Description Of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
        4. 9.2.2.4 SNR and Clock Jitter
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Sharing DRVDD and AVDD Supplies
      2. 9.3.2 Using DC/DC Power Supplies
      3. 9.3.3 Power Supply Bypassing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Grounding
        2. 9.4.1.2 Supply Decoupling
        3. 9.4.1.3 Exposed Pad
        4. 9.4.1.4 Routing Analog Inputs
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.9 Timing Requirements: LVDS and CMOS Modes(1)

Typical values are at 25°C, AVDD = 1.8 V, DRVDD = 1.8 V, sampling frequency = 160MSPS, sine wave input clock, 1.5 VPP clock amplitude, CLOAD = 5 pF(2), and RLOAD = 100 Ω(3), unless otherwise noted. Minimum and maximum values are across the full temperature range: TMIN = –40°C to TMAX = 85°C, AVDD = 1.8 V, and DRVDD = 1.7 V to 1.9 V.
MINNOMMAXUNIT
tAAperture delay0.50.81.1ns
Aperture delay matchingBetween the two channels of the same device±70ps
Variation of aperture delayBetween two devices at the same temperature and DRVDD supply±150ps
tJAperture jitter140fS rms
Wakeup timeTime to valid data after coming out of STANDBY mode50100µs
Time to valid data after coming out of GLOBAL power-down mode100500µs
ADC latency(7)Default latency after reset16Clock cycles
Digital functions enabled (EN DIGITAL = 1)24Clock cycles
DDR LVDS MODE(4)
tSUData setup timeData valid(5) to zero-crossing of CLKOUTP1.52ns
tHData hold timeZero-crossing of CLKOUTP to data becoming invalid(5)0.350.6ns
tPDIClock propagation delayInput clock rising edge cross-over to output clock rising edge cross-over56.17.5ns
LVDS bit clock duty cycleDuty cycle of differential clock, (CLKOUTP-CLKOUTM)49%
tRISE,
tFALL		Data rise time,
Data fall time		Rise time measured from –100 mV to +100 mV
Fall time measured from +100 mV to –100 mV
1MSPS ≤ Sampling frequency ≤ 160MSPS		0.13ns
tCLKRISE,
tCLKFALL		Output clock rise time,
Output clock fall time		Rise time measured from –100 mV to +100 mV
Fall time measured from +100 mV to –100 mV
1MSPS ≤ Sampling frequency ≤ 160MSPS		0.13ns
PARALLEL CMOS MODE
tSUData setup timeData valid(6) to zero-crossing of CLKOUT1.62.5ns
tHData hold timeZero-crossing of CLKOUT to data becoming invalid(6)2.32.7ns
tPDIClock propagation delayInput clock rising edge cross-over to output clock rising edge cross-over4.56.48.5ns
Output clock duty cycleDuty cycle of output clock, CLKOUT
1MSPS ≤ Sampling frequency ≤ 160MSPS		46%
tRISE,
tFALL		Data rise time,
Data fall time		Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ Sampling frequency ≤ 160MSPS		1ns
tCLKRISE,
tCLKFALL		Output clock rise time
Output clock fall time		Rise time measured from 20% to 80% of DRVDD
Fall time measured from 80% to 20% of DRVDD
1MSPS ≤ Sampling frequency ≤ 160MSPS		1ns
(1) Timing parameters are ensured by design and characterization and not tested in production.
(2) CLOAD is the effective external single-ended load capacitance between each output pin and ground
(3) RLOAD is the differential load resistance between the LVDS output pair.
(4) Measurements are done with a transmission line of 100Ω characteristic impedance between the device and the load. Setup and hold time specifications take into account the effect of jitter on the output data and clock.
(5) Data valid refers to a logic high of +100 mV and a logic low of –100 mV.
(6) Data valid refers to a logic high of 1.26 V and a logic low of 0.54 V
(7) At higher frequencies, tPDI is greater than one clock period and overall latency = ADC latency + 1.