JAJSPW8E march   2011  – february 2023 ADS4222 , ADS4225 , ADS4226 , ADS4242 , ADS4245 , ADS4246

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 概要 (続き)
  6. 6 Pin Configuration and Functions
    1.     Pin Functions – LVDS Mode
    2.     Pin Functions – CMOS Mode
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: ADS4246, ADS4245, ADS4242
    6. 7.6  Electrical Characteristics: ADS4226, ADS4225, ADS4222
    7. 7.7  Electrical Characteristics: General
    8. 7.8  Digital Characteristics
    9. 7.9  Timing Requirements: LVDS and CMOS Modes #GUID-C6C0701B-A11B-492F-BD6B-B774F5FE4665/SLAS6895399
    10. 7.10 Serial Interface Timing Characteristics #GUID-3852E7CE-C5B6-42F5-A56A-70AB1B981302/SBAS5097810
    11. 7.11 Reset Timing (Only When Serial Interface Is Used)
    12. 7.12 Typical Characteristics
      1. 7.12.1 ADS4246
      2. 7.12.2 ADS4245
      3. 7.12.3 ADS4242
      4. 7.12.4 ADS4226
      5. 7.12.5 ADS4225
      6. 7.12.6 ADS4222
      7. 7.12.7 General
      8. 7.12.8 Contour
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Drive Circuit Requirements
        2. 8.3.1.2 Driving Circuit
      2. 8.3.2 Clock Input
      3. 8.3.3 Digital Functions
      4. 8.3.4 Gain for SFDR/SNR Trade-off
      5. 8.3.5 Offset Correction
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down
        1. 8.4.1.1 Global Power-Down
        2. 8.4.1.2 Channel Standby
        3. 8.4.1.3 Input Clock Stop
    5. 8.5 Programming
      1. 8.5.1 47
      2. 8.5.2 Parallel Configuration Only
      3. 8.5.3 Serial Interface Configuration Only
      4. 8.5.4 Using Both Serial Interface and Parallel Controls
      5. 8.5.5 Parallel Configuration Details
      6. 8.5.6 Serial Interface Details
        1. 8.5.6.1 Register Initialization
        2. 8.5.6.2 Serial Register Readout
      7. 8.5.7 Digital Output Information
        1. 8.5.7.1 Output Interface
        2. 8.5.7.2 DDR LVDS Outputs
        3. 8.5.7.3 LVDS Buffer
        4. 8.5.7.4 Parallel CMOS Interface
        5. 8.5.7.5 CMOS Interface Power Dissipation
        6. 8.5.7.6 Multiplexed Mode of Operation
        7. 8.5.7.7 Output Data Format
    6. 8.6 Register Maps
      1. 8.6.1 64
      2. 8.6.2 Description Of Serial Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Analog Input
        2. 9.2.2.2 Clock Driver
        3. 9.2.2.3 Digital Interface
        4. 9.2.2.4 SNR and Clock Jitter
      3. 9.2.3 Application Curves
    3. 9.3 Power Supply Recommendations
      1. 9.3.1 Sharing DRVDD and AVDD Supplies
      2. 9.3.2 Using DC/DC Power Supplies
      3. 9.3.3 Power Supply Bypassing
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
        1. 9.4.1.1 Grounding
        2. 9.4.1.2 Supply Decoupling
        3. 9.4.1.3 Exposed Pad
        4. 9.4.1.4 Routing Analog Inputs
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 Device Nomenclature
    2. 10.2 Documentation Support
      1. 10.2.1 Related Documentation
    3. 10.3 サポート・リソース
    4. 10.4 商標
    5. 10.5 静電気放電に関する注意事項
    6. 10.6 用語集
  11. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

Pin Functions – LVDS Mode

GUID-20230214-CA0I-L1JD-XTLN-SFXZWJXHKFVK-low.svg Figure 6-1 ADS4246, ADS4245, and ADS4242
RGC Package
64-Pin VQFN With Exposed Thermal Pad
LVDS Mode (Top View)
GUID-20230214-CA0I-1CDS-WNQ4-DGN7DM2J0W9L-low.svg Figure 6-2 ADS4226, ADS4225, and ADS4222
RGC Package
64-Pin VQFN With Exposed Thermal Pad
LVDS Mode (Top View)
Table 6-1 Pin Functions
PIN TYPE DESCRIPTION
NAME ADS4246, 45,42 ADS4226, 25, 22
AGND 17, 18, 21, 24, 27, 28, 31, 32 17, 18, 21, 24, 27, 28, 31, 32 Input Analog ground
AVDD 16, 22, 33, 34 16, 22, 33, 34 Input Analog power supply
CLKM 26 26 Input Differential clock negative input
CLKOUTM 56 56 Output Differential output clock, complement
CLKOUTP 57 57 Output Differential output clock, true
CLKP 25 25 Input Differential clock positive input
CTRL1 35 35 Input Digital control input pins. Together, they control the various power-down modes.
CTRL2 36 36 Input Digital control input pins. Together, they control the various power-down modes.
CTRL3 37 37 Input Digital control input pins. Together, they control the various power-down modes.
DA0P 41 43 Output Channel A differential output data pair, D0 and D1 multiplexed
DA0M 40 42 Output Channel A differential output data pair, D0 and D1 multiplexed
DA2P 43 45 Output Channel A differential output data D2 and D3 multiplexed
DA2M 42 44 Output Channel A differential output data D2 and D3 multiplexed
DA4P 45 47 Output Channel A differential output data D4 and D5 multiplexed
DA4M 44 46 Output Channel A differential output data D4 and D5 multiplexed
DA6P 47 51 Output Channel A differential output data D6 and D7 multiplexed
DA6M 46 50 Output Channel A differential output data D6 and D7 multiplexed
DA8P 51 53 Output Channel A differential output data D8 and D9 multiplexed
DA8M 50 52 Output Channel A differential output data D8 and D9 multiplexed
DA10P 53 55 Output Channel A differential output data D10 and D11 multiplexed
DA10M 52 54 Output Channel A differential output data D10 and D11 multiplexed
DA12M 54 -- Output Channel A differential output data D12 and D13 multiplexed (ADS424x only)
DA12P 55 -- Output Channel A differential output data D12 and D13 multiplexed (ADS424x only)
DB0P 61 63 Output Channel B differential output data pair, D0 and D1 multiplexed
DB0M 60 62 Output Channel B differential output data pair, D0 and D1 multiplexed
DB2P 63 3 Output Channel B differential output data D2 and D3 multiplexed
DB2M 62 2 Output Channel B differential output data D2 and D3 multiplexed
DB4P 3 5 Output Channel B differential output data D4 and D5 multiplexed
DB4M 2 4 Output Channel B differential output data D4 and D5 multiplexed
DB6P 5 7 Output Channel B differential output data D6 and D7 multiplexed
DB6M 4 6 Output Channel B differential output data D6 and D7 multiplexed
DB8P 7 9 Output Channel B differential output data D8 and D9 multiplexed
DB8M 6 8 Output Channel B differential output data D8 and D9 multiplexed
DB10P 9 11 Output Channel B differential output data D10 and D11 multiplexed
DB10M 8 10 Output Channel B differential output data D10 and D11 multiplexed
DB12P 11 -- Output Channel B differential output data D12 and D13 multiplexed (ADS424x only)
DB12M 10 -- Output Channel B differential output data D12 and D13 multiplexed (ADS424x only)
DRGND 49, PAD 49, PAD Input Output buffer ground. The Thermal PAD is connected to DRGND
DRVDD 1, 48 1, 48 Input Output buffer supply
INM_A 30 30 Input Differential analog negative input, channel A
INM_B 20 20 Input Differential analog negative input, channel B
INP_A 29 29 Input Differential analog positive input, channel A
INP_B 19 19 Input Differential analog positive input, channel B
NC 38, 39, 58, 59
Refer to Figure 7-28, Figure 7-29, and Figure 7-45		 38, 39, 40, 41, 58, 59, 60, 61 — Do not connect, must be floated
RESET 12 12 Input Serial interface RESET input.
When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the software reset option; refer to the Serial Interface Configuration section.
In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150-kΩ pulldown resistor.
SCLK 13 13 Input This pin functions as a serial interface clock input when RESET is low. It controls the low-speed mode selection when RESET is tied high; see Table 8-6 for detailed information. This pin has an internal 150-kΩ pulldown resistor.
SDATA 14 14 Input Serial interface data input; this pin has an internal 150-kΩ pulldown resistor.
SDOUT 64 64 Output This pin functions as a serial interface register readout when the READOUT bit is enabled. When READOUT = 0, this pin is in high-impedance state.
SEN 15 15 Input This pin functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high; see Table 8-7 for detailed information. This pin has an internal 150-kΩ pullup resistor to AVDD.
VCM 23 23 Output This pin outputs the common-mode voltage (0.95 V) that can be used externally to bias the analog input pins