SBAS558C December   2012  – December 2015 ADS42B49

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Description (continued)
  6. 6 ADS424x and ADS422x Family Comparison
  7. 7 Pin Configuration and Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Thermal Information
    5. 8.5  Electrical Characteristics: ADS42B49 (250 MSPS)
    6. 8.6  Electrical Characteristics: General
    7. 8.7  Digital Characteristics
    8. 8.8  Timing Requirements: LVDS and CMOS Modes
    9. 8.9  Serial Interface Timing Characteristics
    10. 8.10 Reset Timing (Only When Serial Interface is Used)
    11. 8.11 LVDS Timings at Lower Sampling Frequencies
    12. 8.12 CMOS Timings at Lower Sampling Frequencies
    13. 8.13 Typical Characteristics
      1. 8.13.1 ADS42B49
      2. 8.13.2 Contour
  9. 9 Parameter Measurement Information
  10. 10Detailed Description
    1. 10.1 Overview
    2. 10.2 Functional Block Diagram
    3. 10.3 Feature Description
      1. 10.3.1 Migrating from the ADS62P49 and ADS4249
      2. 10.3.2 Digital Functions
      3. 10.3.3 Gain for SFDR and SNR Trade-Off
      4. 10.3.4 Offset Correction
    4. 10.4 Device Functional Modes
      1. 10.4.1 Power-Down
        1. 10.4.1.1 Global Power-Down
        2. 10.4.1.2 Channel Standby
        3. 10.4.1.3 Input Clock Stop
      2. 10.4.2 Digital Output Information
        1. 10.4.2.1 Output Interface
        2. 10.4.2.2 DDR LVDS Outputs
        3. 10.4.2.3 LVDS Buffer
        4. 10.4.2.4 Parallel CMOS Interface
        5. 10.4.2.5 CMOS Interface Power Dissipation
        6. 10.4.2.6 Multiplexed Mode of Operation
        7. 10.4.2.7 Output Data Format
      3. 10.4.3 Parallel Configuration Details
    5. 10.5 Programming
      1. 10.5.1 Parallel Configuration Only
      2. 10.5.2 Serial Interface Configuration Only
      3. 10.5.3 Using Both Serial Interface and Parallel Controls
      4. 10.5.4 Serial Interface Details
        1. 10.5.4.1 Register Initialization
        2. 10.5.4.2 Serial Register Readout
    6. 10.6 Register Maps
      1. 10.6.1 Register Description
  11. 11Application and Implementation
    1. 11.1 Application Information
      1. 11.1.1 Driving Circuit
        1. 11.1.1.1 Drive Circuit Requirements
      2. 11.1.2 Clock Input
    2. 11.2 Typical Application
      1. 11.2.1 Design Requirements
      2. 11.2.2 Detailed Design Procedure
        1. 11.2.2.1 Analog Input
        2. 11.2.2.2 Clock Driver
        3. 11.2.2.3 Digital Interface
      3. 11.2.3 Application Curves
  12. 12Power Supply Recommendations
    1. 12.1 Using DC/DC Power Supplies
    2. 12.2 Power Supply Bypassing
  13. 13Layout
    1. 13.1 Layout Guidelines
      1. 13.1.1 Grounding
      2. 13.1.2 Supply Decoupling
      3. 13.1.3 Exposed Pad
      4. 13.1.4 Routing Analog Inputs
    2. 13.2 Layout Example
  14. 14Device and Documentation Support
    1. 14.1 Device Support
      1. 14.1.1 Device Nomenclature
    2. 14.2 Documentation Support
      1. 14.2.1 Related Documentation
    3. 14.3 Community Resources
    4. 14.4 Trademarks
    5. 14.5 Electrostatic Discharge Caution
    6. 14.6 Glossary
  15. 15Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

12 Power Supply Recommendations

The ADS42B49 has three power supplies: two analog (AVDD and AVDD_BUF) and one digital (DRVDD) supply. The AVDD supply has a nominal voltage of 1.9 V. The AVDD_BUF supply has a nominal voltage of 3.3 V. DRVDD supply has a nominal voltage of 1.8 V. Both AVDD supplies are noise sensitive and the digital supply is not.

12.1 Using DC/DC Power Supplies

DC/DC switching power supplies can be used to power DRVDD without issue. Both AVDD supplies can be powered from a switching regulator. Noise and spurs on the AVDD power supply affect the SNR and SFDR of the ADC, and appear near DC and as a modulated component around the input frequency. If a switching regulator is used, it should be designed to have minimal voltage ripple. Supply filtering should be used to limit the amount of spurious noise at the AVDD supply pins. Extra placeholders should be placed on the schematic for additional filtering. Optimize filtering in the final system to achieve the desired performance. The choice of power supply ultimately depends on the system requirements. For instance, if very low phase noise is required, do not use a switching regulator.

12.2 Power Supply Bypassing

Because the ADS42B49 already includes internal decoupling, minimal external decoupling can be used without loss in performance. Decoupling capacitors can help filter external power-supply noise; thus, the optimum number of capacitors depends on the actual application. A 0.1-uF capacitor is recommended near each supply pin. The decoupling capacitors should be placed very close to the converter supply pins.