12-Bit, 1-GSPS Analog-to-Digital Converter
- SLAS669E September 2010 – may 2020 ADS5400-SP
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

12-Bit, 1-GSPS Analog-to-Digital Converter

1 Features

1-GSPS sample rate
12-Bit resolution
2.1 GHz input bandwidth
SFDR = 65 dBc at 1.2 GHz
SNR = 57 dBFS at 1.2 GHZ
7 Clock cycle latency
Interleave friendly: internal adjustments for gain, phase and offset
1.5 - 2 V_PP Differential input voltage, programmable
LVDS-compatible outputs, 1 or 2 bus options
Total power dissipation: 2.2 W
On-chip analog buffer
100-pin ceramic nonconductive tie-bar package
Military temperature range
(–55°C to 125°C T_case)
Processed per internal QML class V assembly/test flow
QML class V qualified, SMD 5962-09240

2 Applications

Test and measurement instrumentation
Ultra-wide band software-defined radio
Data acquisition
Power amplifier linearization
Signal intelligence and jamming
Radar
Engineering Evaluation (/EM) Samples are Available ⁽¹⁾

1. These units are intended for engineering evaluation only. They are processed to a non-compliant flow (e.g. no burn-in, etc.) and are tested to temperature rating of 25°C only. These units are not suitable for qualification, production, radiation testing or flight use. Parts are not warranted for performance on full MIL specified temperature range of -55°C to 125°C or operating life.

3 Description

The ADS5400 is a 12-bit, 1-GSPS analog-to-digital converter (ADC) that operates from both a 5-V supply and 3.3-V supply, while providing LVDS-compatible digital outputs. The analog input buffer isolates the internal switching of the track and hold from disturbing the signal source. The simple 3-stage pipeline provides extremely low latency for time critical applications. Designed for the conversion of signals up to 2 GHz of input frequency at 1 GSPS, the ADS5400 has outstanding low noise performance and spurious-free dynamic range over a large input frequency range.

The ADS5400 is available in a 100-Pin Ceramic Nonconductive Tie-Bar Package. The combination of the ceramic package and moderate power consumption of the ADS5400 allows for operation without an external heatsink. The ADS5400 is built on Texas Instrument's complementary bipolar process (BiCom3) and is specified over the full military temperature range (–55°C to 125°C T_case).

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
ADS5400-SP	HSF (100)	19.05 mm x 19.05 mm

For all available packages, see the orderable addendum at the end of the data sheet.

Block Diagram

4 Revision History

Changes from D Revision (January 2014) to E Revision

Added Device Information table, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. Go
Added table note 1 to the Recommended Operating ConditionsGo
Changed the Thermal Information tableGo
Changed the Layout sectionGo

Changes from C Revision (August 2012) to D Revision

Added /EM bullet to FeaturesGo
Deleted PACKAGE/ORDERING INFORMATION tableGo

5 Pin Configuration and Functions

HSF package(100)

CFP (TBAR) 100-pins

Top View

Pin Functions

PIN		DESCRIPTION
NAME	NO.	DESCRIPTION
AINP, AINN	94, 95	Analog differential input signal (positive, negative). Includes 100-Ω differential load on-chip.
AVDD5	1, 76, 86, 90, 92, 97, 99	Analog power supply (5 V)
AVDD3	2, 7, 9, 85	Analog power supply (3.3 V)
DVDD3	24, 38, 50, 64	Output driver power supply (3.3 V)
AGND	3, 6, 8, 84, 88, 91, 93, 96, 98, 100	Analog Ground
DGND	25, 39, 51, 65	Digital Ground
CLKINP, CLKINN	4, 5	Differential input clock (positive, negative). Includes 160-Ω differential load on-chip.
DA0N, DA0P	46, 47	Bus A, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DA1N–DA10N, DA1P-DA10P	48-49, 52-59, 62-63, 66-73	Bus A, LVDS digital output pairs (bits 1- 10)
DA11N, DA11P	74, 75	Bus A, LVDS digital output pair, most-significant bit (MSB)
CLKOUTAN, CLKOUTAP	60, 61	Bus A, Clock Output (Data ready), LVDS output pair
DB0N, DB0P	40, 41	Bus B, LVDS digital output pair, least-significant bit (LSB) (P = positive output, N = negative output)
DB1N–DB10N, DB1P-DB10P	14-23, 28-37	Bus B, LVDS digital output pairs (bits 1- 10)
DB11N, DB11P	12, 13	Bus B, LVDS digital output pair, most-significant bit (MSB)
CLKOUTBN, CLKOUTBP	26, 27	Bus B, Clock Output (Data ready), LVDS output pair
OVRAN, OVRAP	44, 45	Bus A, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. Becomes SYNCOUTA when SYNC mode is enabled in register 0x05.
OVRBN, OVRBP	42, 43	Bus B, Overrange indicator LVDS output. A logic high signals an analog input in excess of the full-scale range. Becomes SYNCOUTB when SYNC mode is enabled in register 0x05.
RESETN, RESETP	10, 11	Digital Reset Input, LVDS input pair. Inactive if logic low. When clocked in a high state, this is used for resetting the polarity of CLKOUT signal pair(s). If SYNC mode is enabled in register 0x05, this input also provides a SYNC time-stamp with the data sample present when RESET is clocked by the ADC, as well as CLKOUT polarity reset. Includes 100-Ω differential load on-chip.
SCLK	78	Serial interface clock.
SDIO	79	Bi-directional serial interface data in 3-pin mode (default) for programming/reading internal registers. In 4-pin interface mode (reg 0x01), the SDIO pin is an input only.
SDO	80	Uni-directional serial interface data in 4-pin mode (reg 0x01) provides internal register settings. The SDO pin is in high-impedance state in 3-pin interface mode (default).
SDENB	77	Active low serial data enable, always an input. Use to enable the serial interface. Internal 100kΩ pull-up resistor.
VREF	87	Reference voltage input (2V nominal). A 0.1μF capacitor to AGND is recommended, but not required.
ENA1BUS	81⁽¹⁾	Enable single output bus mode (2-bus mode is default), active high. This pin is logic OR'd with addr 0x02h bit<0>.
ENPWD	82⁽¹⁾	Enable Powerdown, active high. Places the converter into power-saving sleep mode when high. This pin is logic OR'd with addr 0x05h bit<6>.
ENEXTREF	83⁽¹⁾	Enable External Reference Mode, active high. Device uses an external voltage reference when high. This pin is logic OR'd with addr 0x05h bit<2>.
VCM	89	Analog input common mode voltage, Output (for DC-coupled applications, nominally 2.5V). A 0.1μF capacitor to AGND is recommended, but not required.

(1) This pin contains an internal ~40kΩ pull-down resistor, to ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

				MIN	MAX	UNIT
Supply voltage	AVDD5 to GND				6	V
	AVDD3 to GND				5	V
	DVDD3 to GND				5	V
	AINP, AINN to GND⁽²⁾	voltage difference between pin and ground		0.5	4.5	V
	AINP to AINN ⁽²⁾	voltage difference between pins, common mode at AVDD5/2	short duration	–0.3	(AVDD5 + 0.3)	V
			continuous AC signal	1.25	3.75	V
			continuous DC signal	1.75	3.25	V
	CLKINP, CLKINN to GND ⁽²⁾	voltage difference between pin and ground		0.5	4.5	V
	CLKINP to CLKINN ⁽²⁾	voltage difference between pins, common mode at AVDD5/2	continuous AC signal	1.1	3.9	V
	CLKINP to CLKINN ⁽²⁾	voltage difference between pins, common mode at AVDD5/2	continuous DC signal	2	3	V
	RESETP, RESETN to GND ⁽²⁾	voltage difference between pin and ground		–0.3	(AVDD5 + 0.3)	V
	RESETP to RESETN ⁽²⁾	voltage difference between pins	continuous AC signal	1.1	3.9	V
	RESETP to RESETN ⁽²⁾	voltage difference between pins	continuous DC signal	2	3	V
	Data/OVR Outputs to GND ⁽²⁾	voltage difference between pin and ground		–0.3	(DVDD3 + 0.3)	V
	SDENB, SDIO, SCLK to GND⁽²⁾			–0.3	(AVDD3 + 0.3)
	ENA1BUS, ENPWD, ENEXTREF to GND⁽²⁾			–0.3	(AVDD5 + 0.3)
Operating case temperature range				–55	125	°C
Maximum junction temperature, T_J					150	°C
Storage temperature range				–65	150	°C

(1) Stresses above these ratings may cause permanent damage. Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is not implied. Kirkendall voidings and current density information for calculation of expected lifetime is available upon request.

(2) Valid when supplies are within recommended operating range.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.