The ADS58J89 is a high-linearity, quad-channel, 14-bit, 250/500-MSPS IF (intermediate frequency) receiver. The four channels contain 500MSPS 14-bit ADCs followed by signal processing for wireless infrastructure systems. The channels can be configured in various modes depending on bandwidth, resolution and sample time requirements. The signal processing block contains selectable modes for decimation filters, SNR Boost filters, resolution versus time and time-division duplex (TDD) burst mode. Designed for high antenna count systems, the 4 channels provides high bandwidth and linearity to multi-channel receivers in a small footprint. The device can be dual function as traffic receiver and power amplifier linearization feedback path in TDD systems.
Key Specifications:
PART NUMBER | PACKAGE | MAX OUTPUT RATE |
---|---|---|
ADS58J89 | VQFN (64) | 500 MSPS |
DATE | REVISION | NOTES |
---|---|---|
November 2014 | * | Initial release. |
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
INPUT OR REFERENCE | |||
INAP, INAM | 63, 62 | I | Differential analog input for channel A |
INBP, INBM | 58, 59 | I | Differential analog input for channel B |
INCP, INCM | 18, 19 | I | Differential analog input for channel C |
INDP, INDM | 23, 22 | I | Differential analog input for channel D |
VCM | 16 | O | Common mode output voltage to bias analog inputs, Vcm = 2.0 V |
VREF | 15 | O | Voltage reference output. A 0.1-µF bypass capacitor to ground close to the pin is recommended |
CLOCK/SYNC | |||
CLKINP, CLKINM | 9, 8 | I | Differential clock input for channel |
SYSREFABP, SYSREFABM | 6, 5 | I | LVDS input with internal 100-Ω termination. External SYSREF input for channels A, B, C, and D |
SYSREFCDP, SYSREFCDM | 11, 12 | I | LVDS input with internal 100-Ω termination. External SYSREF input for channels C and D if output rate of channel A/B is different from channel C/D. Can be configured to trigger input for burst modes with SPI register write. Can be used as differential input or two single-ended inputs (SYSREFCDP becomes TRIGGERAB and SYSREFCDM becomes TRIGGERCD) for channel A/B and channel C/D. |
CONTROL OR SERIAL | |||
ENABLE | 14 | I | Chip enable. Active high. Power down functionality can be configured through SPI register setting and exercised using the ENABLE pin. Internal 51-kΩ pulldown resistor. |
SCLK | 3 | I | Serial interface clock input |
SDATA | 2 | I/O | Bidirectional serial data in 3-pin mode. In 4-pin interface, the SDATA pin is an input only. |
SDENb | 4 | I | Serial interface enable |
SDOUT | 1 | O | Serial interface data output |
SRESETb | 13 | I | Hardware reset. Active low. Initializes internal registers during high to low transition. This pin has an internal 51-kΩ pullup resistor. |
DATA OUTPUT INTERFACE | |||
DA[0,1]P, DA[0,1]M | 55, 54, 52, 51 | O | JESD204B output interface for channel A |
DB[0,1]P, DB[0,1]M | 46, 45, 43, 42 | O | JESD204B output interface for channel B |
DC[0,1]P, DC[0,1]M | 26, 27, 29, 30 | O | JESD204B output interface for channel C |
DD[0,1]P, DD[0,1]M | 35, 36, 38, 39 | O | JESD204B output interface for channel D |
OVRA | 50 | I/O | Fast over-range indicator channel A. In burst mode can be configured to TRIGGERAB input. |
OVRB | 49 | O | Fast over-range indicator channel B. In burst mode can be configured to TRDY output. |
OVRC | 31 | I/O | Fast over-range indicator channel C. In burst mode can be configured to TRIGGERCD input. |
OVRD | 32 | O | Fast over-range indicator channel D. In burst mode can be configured to TRDY output. |
SYNCbABP, SYNCbABM | 47, 48 | I | SYNCb input for JESD204B interface for channel A/B, internal 100-Ω termination |
SYNCbCDP, SYNCbCDM | 34, 33 | I | SYNCb input for JESD204B interface for channel C/D, internal 100-Ω termination |
POWER SUPPLY | |||
AVDDC | 7, 10 | I | Clock 1.8-V power supply |
AVDD18 | 21, 24, 57, 60 | I | Analog 1.9-V power supply |
AVDD33 | 17, 20, 61, 64 | I | Analog 3.3-V power supply |
DVDD | 25, 56 | I | Digital 1.8-V power supply |
GND | PowerPAD™ | I | Ground |
IOVDD | 28, 37, 44, 53 | I | JESD204B output interface 1.8-V power supply |
PLLVDD | 40, 41 | I | PLL 1.8-V power supply |
MIN | MAX | UNIT | ||
---|---|---|---|---|
Supply voltage | AVDD33 | –0.3 | 3.6 | V |
AVDD18 | –0.3 | 2.1 | ||
AVDDC | –0.3 | 2.1 | ||
DVDD | –0.3 | 2.1 | ||
IOVDD | –0.3 | 2.1 | ||
PLLVDD | –0.3 | 2.1 | ||
Voltage between AGND and DGND | –0.3 | 0.3 | V | |
Voltage applied to input pins | INAP, INBP, INCP, INDP, INAM, INBM, INCM, INDM | –0.3 | 3 | V |
CLKINP, CLKINM | –0.3 | AVDD18 + 0.3 V | ||
SYNCbABP, SYNCbABM, SYNCbCDP, SYNCbCDM | –0.3 | AVDD18 + 0.3 V | ||
SYSREFABP, SYSREFABM, SYSREFCDP, SYSREFCDM | –0.3 | AVDD18 + 0.3 V | ||
SCLK, SDENb, SDATA, SRESETb, ENABLE | –0.3 | DVDD + 0.5 V | ||
TA | Operating free-air temperature | –40 | 85 | ºC |
TJ | Operating junction temperature(2) | 125 | ºC |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Tstg | Storage temperature | –65 | 150 | °C | |
VESD | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | –2 | 2 | kV |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
ADC clock frequency | 250 | 500 | MSPS | |||
Resolution | 14 | 14 | bits | |||
Supply | AVDD33 | 3.15 | 3.3 | 3.45 | V | |
AVDD18 | 1.8 | 1.9 | 2.0 | |||
AVDDC | 1.7 | 1.8 | 1.9 | |||
DVDD | 1.7 | 1.8 | 1.9 | |||
IOVDD | 1.7 | 1.8 | 1.9 | |||
PLLVDD | 1.7 | 1.8 | 1.9 | |||
TA | Operating free-air temperature | –40 | 85 | °C | ||
TJ | Operating junction temperature | 125 | °C |
Thermal Metric(1) | RGC (64 PINS) | UNIT | |
---|---|---|---|
RΘJA | Junction-to-ambient thermal resistance | 23.5 | °C/W |
RΘJC(top) | Junction-to-case, top | 7.0 | |
RΘJB | Junction-to-board thermal resistance | 2.6 | |
φJT | Junction-to-top of package | 0.1 | |
φJB | Junction-to-board characterization parameter | 2.6 | |
RΘJC(bot) | Junction-to-case, bottom | 0.3 |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
POWER SUPPLY | |||||||
IAVDD33 | 3.3-V analog supply current | 500 | mA | ||||
IAVDD18 | 1.9-V analog supply current | 320 | mA | ||||
IAVDDC | 1.8-V clock supply current | 18 | mA | ||||
IDVDD | 1.8-V digital supply current | 4-channel SNR boost | 472 | mA | |||
4-channel decimation filter | 323 | ||||||
4-channel burst mode | 324 | ||||||
2-channel burst mode, 2-channel SNR boost | 398 | ||||||
2-channel decimation filter, 2-channel burst mode | 324 | ||||||
2-channel decimation filter, 2-channel, discard every other sample | 289 | ||||||
IIOVDD | I/O voltage supply current | 2 lanes per ADC | 373 | mA | |||
1 lane per ADC | 185 | ||||||
IPLLVDD | PLL voltage supply current | 42 | mA | ||||
Pdis | Total power dissipation | 4-channel SNR boost | 3.94 | W | |||
4-channel Burst mode | 3.67 | ||||||
4-channel decimation filter | 3.34 | ||||||
4-channel decimation filter, 1 lane per ADC | 3.27 | 3.5 | |||||
2-channel SNR Boost, 2-channel burst mode | 3.81 | ||||||
2-channel decimation filter, 2-channel burst mode | 3.51 | ||||||
2-channel decimation filter, 2-channel, discard every other sample | 3.28 | ||||||
Deep sleep mode power | 791 | mW | |||||
Wake-up time from deep sleep mode | SNR > 60 dB | 1.4 | ms | ||||
Light sleep mode power | 1.68 | W | |||||
Wake-up time from light sleep mode | SNR > 60 dB | 8 | µs | ||||
ANALOG INPUTS | |||||||
Differential input full-scale | 1.0 | 1.25 | 1.5 | Vpp | |||
Input common mode voltage | Vcm ± 50 mV | V | |||||
Input resistance | Differential at DC | 1 | kΩ | ||||
Input capacitance | Each input to GND | 2.75 | pF | ||||
VCM | Common mode voltage output | 2.18 | V | ||||
Analog input bandwidth (–3 dB) | 900 | MHz | |||||
CHANNEL-TO-CHANNEL ISOLATION | |||||||
Crosstalk(1) | Near channel | ƒIN = 170 MHz | 85 | dB | |||
Far channel | ƒIN = 170 MHz | 95 | |||||
CLOCK INPUT | |||||||
Input clock frequency | 250 | 2000(2) | MHz | ||||
Input clock amplitude | 0.4 | 1.5 | Vpp | ||||
Input clock duty cycle | 45% | 50% | 55% | ||||
Internal clock biasing | 0.9 | V |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SNR | Signal-to-noise ratio | ƒIN = 10 MHz | 68.3 | dBFS | |||
ƒIN = 100 MHz | 68.2 | ||||||
ƒIN = 170 MHz | 65 | 68.2 | |||||
ƒIN = 310 MHz | 67.6 | ||||||
ƒIN = 450 MHz | 66.8 | ||||||
HD2 | Second harmonic distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 75 | 85 | |||||
ƒIN = 310 MHz | 85 | ||||||
ƒIN = 450 MHz | 75 | ||||||
HD3 | Third harmonic distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 75 | 85 | |||||
ƒIN = 310 MHz | 85 | ||||||
ƒIN = 450 MHz | 85 | ||||||
SFDR (Non-HD2, Non-HD3) |
Spur free dynamic range (excluding HD2 and HD3) |
ƒIN = 10 MHz | 95 | dBc | |||
ƒIN = 100 MHz | 95 | ||||||
ƒIN = 170 MHz | 75 | 95 | |||||
ƒIN = 310 MHz | 90 | ||||||
ƒIN = 450 MHz | 85 | ||||||
IMD3 | 2F1-F2, 2F2-F1, Ain = –7 dBFS | FIN = 169 and 171 MHz | 93 | dBFS |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|---|---|
SNR | Signal-to-Noise Ratio | SNR Boost (150-MHz bandwidth) | ƒIN = 100 MHz | 65.7 | dBFS | ||
ƒIN = 170 MHz | 65.7 | ||||||
ƒIN = 350 MHz | 65 | ||||||
Burst Mode (14 bit) | ƒIN = 10 MHz | 65.3 | dBFS | ||||
ƒIN = 100 MHz | 65.2 | ||||||
ƒIN = 170 MHz | 65.1 | ||||||
ƒIN = 370 MHz | 64.7 | ||||||
ƒIN = 450 MHz | 64.6 | ||||||
HD2 | Second Harmonic Distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 85 | ||||||
ƒIN = 370 MHz | 75 | ||||||
ƒIN = 450 MHz | 75 | ||||||
HD3 | Third Harmonic Distortion | ƒIN = 10 MHz | 85 | dBc | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 85 | ||||||
ƒIN = 370 MHz | 78.3 | ||||||
ƒIN = 450 MHz | 85 | ||||||
SFDR (Non-HD2, Non-HD3) |
Spur Free Dynamic Range (excluding HD2 and HD3) |
ƒIN = 10 MHz | 85 | dBFS | |||
ƒIN = 100 MHz | 85 | ||||||
ƒIN = 170 MHz | 85 | ||||||
ƒIN = 370 MHz | 83 | ||||||
ƒIN = 450 MHz | 83 | ||||||
IMD3 | 2F1-F2, 2F2-F1, Ain = –7 dBFS | FIN = 169 and 171 MHz | 87 | dBFS |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
Aperture jitter, RMS | 98 | fs rms | |||
Data latency | 38 | Sample clock cycles | |||
Fast over-range (OVR) latency | 6 | ||||
tPDI | Clock aperture delay | 1.1 | ns |
PARAMETER | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|
DIGITAL OUTPUTS: JESD204B INTERFACE (DA[0,1], DB[0,1], DC[0,1], DD[0,1]) |
|||||
Output differential voltage, |VOD| | 450 | 577 | 750 | mV | |
Transmitter short circuit current | Transmitter terminals shorted to any voltage between –0.25 and 1.45 V | 45 | mA | ||
Single ended output impedance | 50 | Ω | |||
Output capacitance | Output capacitance inside the device, from either output to ground | 2 | pF | ||
Unit interval, UI | 5.0 Gbps | 200 | ps | ||
Rise and fall times | 110 | ps | |||
Output jitter | 57 | ps | |||
Serial output data rate | 5.0 | Gbps |
MIN | TYP | MAX | UNIT | ||
---|---|---|---|---|---|
DIGITAL INPUTS: SRESETb, SCLK, SDENb, SDATA, ENABLE, OVRA, OVRC, SYSREFCDP, SYSREFCDM |
|||||
High-level input voltage | All digital inputs support 1.8-V and 3.3-V logic levels | 1.2 | V | ||
Low-level input voltage | 0.4 | V | |||
High-level input current | 50 | µA | |||
Low-level input current | –50 | µA | |||
Input capacitance | 4 | pF | |||
DIGITAL OUTPUTS: SDOUT, OVRA, OVRB, OVRC, OVRD |
|||||
High-level output voltage | ILoad = –100 µA | DVDD – 0.2 | DVDD | V | |
Low-level output voltage | 0.2 | V | |||
DIGITAL INPUTS: SYNCbABP/M, SYNCbCDP/M, SYSREFABP/M, SYSREFCDP/M |
|||||
Input voltage VID | 250 | 350 | 450 | mV | |
Input common mode voltage VCM | 0.4 | 0.9 | 1.4 | V | |
tS_SYSREFxx | Referenced to rising edge of input clock | 100 | ps | ||
tH_SYSREFxx | Referenced to rising edge of input clock | 100 | ps |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
t1 | Power-on delay | Delay from power up to active-low RESET pulse | 3 | ms | ||
t2 | Reset pulse duration | Active-low RESET pulse duration | 20 | ns | ||
t3 | Register write delay | Delay from RESET disable to SDENb active | 100 | ns |
Fin = 10 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.29 dBFS | SFDR = 84.72 dBc |
Fin = 170 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.34 dBFS | SFDR = 91.62 dBc |
1-lane 2x decimation | Ain = –1 dBFS |
1-lane 2x decimation | Fin = –170 MHz |
1-lane 2x decimation | Fin = –170 MHz |
1-lane 2x decimation | Ain = –1 dBFS |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
Fin = 170 MHz | 1-MHz spacing | 1-lane 2x decimation |
Ain = –7 dBFS | 60 to 100 MHz shown |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
2-lane burst mode | Ain = –1 dBFS |
2-lane burst mode | Ain = –1 dBFS | Fin = 170 MHz |
2-lane SNR boost mode | Ain = –1 dBFS | |
Blackman-Harris filter |
2-lane SNR boost mode | Ain = –1 dBFS | Fin = 170 MHz | ||
Fin = 100 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.40 dBFS | SFDR = 82.50 dBc |
Fin = 230 MHz | 1-lane 2x decimation | Ain = –1 dBFS |
SNR = 65.16 dBFS | SFDR = 76.83 dBc |
1-lane 2x decimation | Ain = –1 dBFS |
1-lane 2x decimation | Fin = –170 MHz |
1-lane 2x decimation | Fin = –170 MHz |
1-lane 2x decimation | Ain = –1 dBFS |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
1-lane 2x decimation | Ain = –1 dBFS | Fin = 170 MHz |
AVDD18 = 1.9 V | AVDD33 = 3.3 V | Other supplies = 1.8 V |
Ain = –1 dBFS | Fin = 170 MHz |
2-lane burst mode | Ain = –1 dBFS | Fin = 170 MHz |
SNR = 65.26 dBFS | SFDR = 90.42 dBc |
2-lane burst mode | Ain = –1 dBFS |
2-lane SNR boost mode | Ain = –1 dBFS | Fin = 170 MHz |
Blackman-Harris filter |
2-lane SNR boost mode | Ain = –1 dBFS | |
Blackman-Harris filter |