8.1.1 SNR and Clock Jitter

The signal-to-noise ratio of the channel is limited by three different factors: the quantization noise is typically not noticeable in pipeline converters and is 84 dB for a 14-bit channel. The thermal noise limits the SNR at low input frequencies while the clock jitter sets the SNR for higher input frequencies.

Equation 2.

Calculate the SNR limitation due to sample clock jitter using the following:

Equation 3.

The total clock jitter (t_Jitter) has two components – the internal aperture jitter (85 fs for ADS58J89), which is set by the noise of the clock input buffer, the external clock jitter, and the jitter from the analog input signal. Calculate total clock jitter using the following:

Equation 4.

External clock jitter can be minimized by using high quality clock sources and jitter cleaners, as well as bandpass filters at the clock input while a faster clock slew rate improves the channel aperture jitter.

The ADS58J89 has a thermal noise of 66 dBFS and internal aperture jitter of 98 fs. The SNR depending on amount of external jitter for different input frequencies is shown in Figure 107.

Figure 107. SNR vs Input Frequency and External Clock Jitter

8.2.1 Design Requirements

The ADS58J89 requires a fully differential analog input with a full-scale range not to exceed 1.25 V peak to peak, biased to a common mode voltage of 2.0 V. In addition the input circuit must provide proper transmission line termination (or proper load resistors in an amplifier-based solution) so the input of the impedance of the ADC analog inputs should be considered as well.

The clocking solution will have a direct impact on performance in terms of SNR, as shown in Figure 107. The ADS58J89 is capable of a typical SNR of 66 dBFS for input frequencies of about 100 MHz (in 14-bit burst mode), so we will want to have a clocking solution that can preserve this level of performance.

8.2.2 Detailed Design Procedure

The ADS58J89 has an input bandwidth of approximately 900 MHz, but we will consider an application involving the first or second Nyquist zones, so we will limit the frequency bandwidth here to be under 250 MHz. We will also consider a 50-ohm signal source, so the proper termination would be 50-Ω differential. As seen in Figure 110 and Figure 111, the input impedance of the analog input at 250 MHz is large compared to 50 Ω, so the proper termination can be 50-Ω differential as shown in Figure 108. Splitting the termination into two 25-Ω resistors with an AC capacitor to ground provides a path to filter out any ripple on the common mode that may result from any amplitude or phase imbalance of the differential input, improving SFDR performance. The ADS58J89 provides a VCM output that may be used to bias the input to the desired level, but as seen in Figure 52 the signal is internally biased inside the ADC so an external biasing to VCM is not required. If an external biasing to VCM were to be employed, the VCM voltage may be applied to the mid-point of the two 25-Ω termination resistors in Figure 108.

For the clock input, Figure 107 shows the SNR of the device above 100 MHz begins to degrade with external clock jitter of greater than 100 fs rms, so we will recommend the clock source be limited to approximately 100 fS of rms jitter. For the ADS58J89 EVM, the LMK04828 clock device is capable of providing a low-jitter sample clock as well as providing the SYSREF signal required as shown in Figure 47 and Figure 48, so that clocking device is one good choice for the clocking solution for the ADS58J89.

8.2.3 Application Curves

Figure 110 and Figure 111 show the differential impedance between the channel INP and INM pins. The impedance is modeled as a parallel combination of RIN and CIN (RIN || 1 / jwCIN).

Figure 110. Equivalent R

Figure 111. Equivalent C