7.3.1 Decimation by 2 (250 MSPS Output)

Each channel has a digital filter in the data path as shown in Figure 39. The filter can be programmed as a low-pass or high-pass filter and the normalized frequency response of both filters is shown in Figure 40.

Figure 39. 2x Decimation Filter

The decimation filter response has a 0.1-dB pass band ripple with approximately 41% pass-band bandwidth. The stop-band attenuation is approximately 40 dB.

Figure 40. Decimation Filter Response

Figure 41. Decimation Filter Response Passband Ripple Detail

7.3.2 Over-Range Indication

The ADS58J89 provides a fast over-range indication on the OVRA, OVRB, OVRC, and OVRD pins. The fast OVR is triggered if the input voltage exceeds the programmable over-range threshold and is output after just 6 clock cycles, enabling a quicker reaction to an over-range event. The OVR threshold can be configured using SPI register writes.

The input voltage level at which the overload is detected is referred to as the threshold and is programmable using the over-range threshold bits.

The threshold at which fast OVR is triggered is (full-scale × [the decimal value of the FAST OVR THRESH bits] / 8). After reset, the default value of the over-range threshold is set to 7 (decimal), which corresponds to a threshold of 1.12 dB below full scale (20 × log(7/8)).

Because the fast over-range indicator is single-ended LVCMOS logic, the ADS58J89 device can be configured through the SPI register write to keep the over-range indicator asserted high for an extra one, two, or four clock cycles. This longer assertion of the signal ensures the processor can capture the over-range event.

Figure 42. Fast Over Range Output Timing

The ADS58J89 device also provides the fast over-range indication bit in the JESD204B output data stream.

Figure 43. Sample Data and Status Bit Format

7.3.3 JESD204B Interface

The ADS58J89 supports device subclass 1 with a maximum output data rate of 5.0 Gbps for each serial transmitter. It allows independent JESD204B format configuration for channel A and B and channel C and D.

An external SYSREF signal is used to align all internal clock phases and the local multi-frame clock to a specific sampling clock edge. This allows synchronization of multiple devices in a system and minimizes timing and alignment uncertainty. SYNCbAB input is used to control all the JESD204B SerDes blocks for channel A and B while SYNCbCD is used to control channel C and D. If the same LMFS configuration is used for all four channels, the SYNCbAB and SYNCbCD signals can be tied together externally and driven from the same source.

Depending on the channel output data rate, the JESD204B output interface can be operated with either 1 or 2 lanes per single channel. The JESD204B setup and configuration of the frame assembly parameters are controlled via SPI interface.

The JESD204B transmitter block consists of the transport layer, the data scrambler and the link layer. The transport layer maps the channel output data into the selected JESD204B frame data format and manages if the channel output data or test patterns are being transmitted. The link layer performs the 8b/10b data encoding as well as the synchronization and initial lane alignment using the SYNCb input signal. Optionally, data from the transport layer can be scrambled.

Figure 44. JESD204B Lane Assignment

Figure 45. JESD204B Block

7.3.3.1 JESD204B Initial Lane Alignment (ILA)

The ILA process is started by the receiving device by deasserting the SYNCb signal. Upon detecting a logic low on the SYNCbAB input pins, the ADS58J89 device starts transmitting comma (K28.5) characters on channels A and B to establish code group synchronization. Upon detecting a logic high on the SYNCbCD input pins, the ADS58J89 device starts transmitting comma (K28.5) characters on channels C and D to establish code group synchronization.

After synchronization is completed, the receiving device asserts the SYNCb signal and the ADS58J89 starts the ILA sequence with the next local multi-frame clock boundary. The ADS58J89 device transmits 4 multi-frames each containing K frames (K is SPI programmable). Each of the multi-frames contains the frame start and end symbols and the second multi-frame also contains the JESD204 link configuration data.

Figure 46. Initial Lane Assignment Format

7.3.4 SYSREF Clocking Schemes

Periodic: The SYSREF signal is always on. This mode is supported, but not recommended as the continuous SYSREF signal appears like an additional clock input, which can cause clock mixing spurs in the channel output spectrum.

Gapped-Periodic (recommended): A periodic SYSREF signal is presented to the ADS58J89 SYSREF inputs for a very short period of time. This configuration requires a DC-coupled SYSREF connection for proper operation. Most of the time the SYSREF signal is in a logic-low state, and thus cannot cause any glitches and spurs in the channel output spectrum.

Pulse/One Shot (recommended): A single SYSREF reset pulse is used to synchronize the ADS58J89. The ADS58J89 device requires a minimum of 3 SYSREF pulses to complete the synchronization phase. The SYSREF signal is in a logic-low state most of the time, and thus cannot cause any glitches and spurs in the channel output spectrum. Special attention should be given to ensure the single pulse meets required the SYSREF input setup and hold time.

7.3.5 Split-Mode Operation

The ADS58J89 provides several different options to interface it to the digital processor or processors. If the ADS58J89 device is operated in split sampling rate (2 channels at 500-MSPS output rate and 2 channels at 250-MSPS output rate), then it requires dual SYSREF (SYSREFAB and SYSREFCD) and dual SYNC (SYNCbAB and SYNCbCD).

Subclass 1 – Deterministic Latency: The device clock and synchronous SYSREF signal are provided by the timing unit to the ADS58J89 and the processor. The processor controls the SYNCb input signals for the JESD204B state machine for all four channels. In case the ADS58J89 is connected to two different processors, the differential SYNCb inputs of the ADS58J89 can be configured to two single-ended inputs where each pin controls the JESD204B state machine of the two corresponding channels.

Figure 47. Four Channel and Dual Two Channel Usage

Split Mode Operation: If the ADS58J89 device is operated with 2-channel output at 500 MSPS and 2-channel output at 250 MSPS, then dual SYSREF (SYSREFAB for channel A and B, SYSREFCD for channel C and D) as well as dual SYNC (SYNCbAB for channel A and B, SYNCbCD for channel C and D) is required to ensure normal operation because the JESD204B link configuration is different for the two channel pairs.

Figure 48. Dual SYSREF Usage

7.3.6 Eye Diagram Information

Figure 49 and Figure 50 is the measured eye diagram at 2.5 and 5Gbps output data rate, respectively. These are overlaid with the JESD204B LV-OIF-6G-SR specification.

Figure 49. 2.5 Gbps Eye Diagram

Figure 50. 5.0 Gbps Eye Diagram

7.3.7 Analog Inputs

The ADS58J89 analog signal inputs are designed to be driven differentially. The analog input pins have internal analog buffers that drive the sampling circuit. As a result of the analog buffer, the input pins present a high-impedance input across a very-wide frequency range to the external driving source, which enables great flexibility in the external analog filter design as well as excellent 50-Ω matching for RF applications. The buffer also helps isolate the external driving circuit from the internal switching currents of the sampling circuit, which results in a more constant SFDR performance across input frequencies.

The common-mode voltage of the signal inputs is internally biased to 2 V using 500-Ω resistors, which allows for AC coupling of the input drive network. Each input pin (INP, INM) must swing symmetrically between (VCM + 0.3125 V) and (VCM – 0.3125 V), resulting in a 1.25-Vpp (default) differential input swing. The input sampling circuit has a 3-dB bandwidth that extends up to 900 MHz.

Figure 51. Normalized Input Bandwidth

Figure 52. Equivalent Analog Input Circuit

7.3.8 Clock Inputs

The ADS58J89 clock input can be driven differentially with a sine wave or LVPECL source with little or no difference in performance. The common mode voltage of the clock input is set to 0.9 V using internal 2-kΩ resistors. This allows for AC coupling of the clock inputs. The termination resistors should be placed as close as possible to the clock inputs in order to minimize signal reflections and jitter degradation.

Figure 53. Equivalent Clock Input Circuit

7.3.9 Input Clock Divider

The ADS58J89 is equipped with two internal dividers on the clock input – one on channel AB and one on channel CD. The clock divider allows operation with a faster input clock simplifying the system clock distribution design. The clock dividers can be bypassed (/1) for operation with a 500-MHz clock while /2 option supports a maximum input clock of 1 GHz and the /4 option a maximum input clock frequency of 2 GHz. Different divider options can be selected for channel AB and channel CD clock output. By default the divider output of channel AB block is routed to all 4 channels but the configuration can be customized with different SPI register settings to use either the channel AB or CD divider blocks for any two channels.

Figure 54. Input Clock Divider

7.3.10 Power-Down Control

The power down functions of the ADS58J89 can be controlled either through the parallel control pin (ENABLE) or through a SPI register setting. Power-down modes for the different channels as well as for the JESD204B interface are supported.

The ADS58J89 supports the following power-down modes. The analog sleep mode configurations are in register 0x05/06 and the JESD204b sleep mode configurations are in register 0x1E and 0x1F.

Control power-down function through ENABLE pin:

1. Configure power-down mode in register 0x05 and 0x1E
2. Normal operation: ENABLE pin high
3. Power-down mode: ENABLE pin low

Control power-down function through SPI (ENABLE pin always high):

1. Assign power-down mode in register 0x06 and 0x1F
2. Normal operation: 0x06 and 0x1F are 0xFFFF
3. Power-down mode: configure power down mode in register 0x06 and 0x1F

7.3.11 Device Configuration

The serial interface (SIF) included in the ADS58J89 is a simple 3- or 4-pin interface. In normal mode, 3 pins are used to communicate with the device. There is an enable (SDENb), a clock (SCLK), and a bidirectional IO port (SDATA). If the user would like to use the 4-pin interface, one write must be implemented in the 3-pin mode to enable 4-pin communications. In this mode, the SDOUT pin becomes the dedicated output. The serial interface has an 8-bit address word and a 16-bit data word. The first rising edge of SCLK after SDENb goes low will latch the read or write bit. If a high is registered, then a read is requested, if it is low, then a write is requested. SDENb must be brought high again before another transfer can be requested.

7.3.12 JESD204B Interface Initialization Sequence

After power-up, the internal JESD204B digital block must be initialized with the following sequence of steps:

1. Set JESD RESET AB/CD and JESD INIT AB/CD to 0 (address 0x0D, value 0x0000)
2. Set JESD INIT AB/CD to 1 (0x0D, 0x0202)
3. Set JESD RESET AB/CD to 1 (0x0D, 0x0303)
4. Configure all other JESD register and clock settings. If those settings change later on, this initialization sequence must be repeated.
5. Set JESD RESET AB/CD to 0 (0x0D, 0x0202)
6. Set JESD RESET AB/CD to 1 (0x0D, 0x0303)
7. Wait for two SYSREF pulses
8. Set JESD INIT AB/CD to 0 (0x0D, 0x0101)

7.3.13 Device and Register Initialization

After power-up, the internal registers must be initialized to their default values through a hardware reset by applying a low pulse on the SRESETb pin (of width greater than 10 ns), as shown in Figure 1. If required later during operation, the serial interface registers can be cleared by applying:

• Another hardware reset using the SRESETb pin
• A software reset (bit D0 in register 0x00). This setting resets the internal registers to the default values and then self-resets the RESET bit (D0) back to 0. In this case, the RESET pin is kept high.

7.4.1 Operating Modes

Table 5 details the five different operating modes. A pair of channels (channel A and B and channel C and D) can be configured in the same operating mode.

7.4.2 Mode Configuration

Table 6 shows examples for different mode configurations for channel A/B and channel C/D regarding input options for SYSREF as well as the trigger for the different burst mode options. Each channel pair (A/B and C/D) can support each mode for 250-MSPS and 500-MSPS output.

7.4.3 Output Format

Table 7 provides detailed information on how the MSB or LSB get aligned for the different output data rates and resolution in the different operating modes.

7.4.4 Burst Mode of Every Other Sample (250 MSPS Output)

In this mode, the channel is sampling at full sampling rate but the output only transmits every other sample with burst mode. During burst mode operation the output is alternated between low resolution 11-bit and high resolution 12- or 14-bit output. The burst mode operation can be configured to auto or manual trigger (see Burst Mode).

Figure 55. Timing Diagram Burst Mode of Every Other Sample

7.4.5 SNR Boost (500 MSPS Output)

In this mode, the channel output data is truncated to 9-bit resolution and the quantization noise is shaped using TI SNR Boost 3G technology. The SNR Boost passband bandwidth maximum is 150 MHz at 500 MSPS centered at the mid-point of the Nyquist zone.

Figure 56. SNR Boost Noise Shape Response

7.4.6 Burst Mode

The ADS58J89 supports TI’s next generation burst mode technology which can be used for the DPD feedback path as well for the receive path (TDD burst mode) in TDD applications. In receive mode, the TDD burst mode is used to support very wide band and high resolution or duty cycle operation. Both modes can also be used simultaneously where two channels operate in burst mode and two channels in TDD burst mode.

In burst mode operation, the ADS58J89 alternatively transmits low resolution (11 bit for 250 MSPS operation and 9 bit for 500 MSPS operation, LSBs are set to 0) and high resolution (11-, 12-, or 14-bit) output data and can be configured via SPI register writes. The number of low and high resolution samples is configured through programmable counters.

7.4.6.1 Burst Mode Counters

The ADS58J89 provides eight independent counters each for channel A and B and channel C and D for burst mode operation. The TDD burst mode employs all eight counters (four for the low resolution samples and four for the high resolution samples) while the normal burst mode uses only H₁ and L₁. Each count corresponds to four samples and each counter can be programmed through a 22-bit register entry (1 to 4194303).

The counter values can be updated at any time, but the update does not go into effect until the start of the next burst mode cycle with low resolution output data (L₁). After programming the counters, the ADS58J89 calculates the corresponding duty cycle for the selected high resolution output. If the duty cycle violates the limits, the digital outputs are limited to low resolution output.

Equation 1.

The duty cycle limits per selected high resolution output is shown in Table 8.

Table 8. Burst Mode Maximum Allowed Duty Cycle

Maximum Allowed Duty Cycle (High : Low Resolution Output)	500 MSPS	250 MSPS
14 bit	1/3	1/1
12 bit	2/3	4/1
11 bit	3/2	–

7.4.6.5 Manual Trigger Mode

Upon enabling manual trigger mode, the ADS58J89 starts transmission of low resolution data. As soon as the L₁ counter is finished, the manual trigger is unlocked and the high resolution output H₁ or burst mode sequence of H₁, L₂, H₂, L₃, H₃, L₄, H₄, L₁ can be triggered. After the low resolution counter L₁ is finished, the next high resolution output or burst mode sequence can be triggered again. The HRES flag is embedded in the JESD204B output data stream. The counter values can be updated until a new burst mode cycles starts with transmission of low resolution samples.

See Figure 57 for an example of normal burst mode with manual trigger.

Figure 57. Burst Mode Duty Cycle Timing

See Figure 58 for an example of TDD burst mode with manual trigger:

Figure 58. TDD Burst Mode Duty Cycle Timing

7.4.6.6 Auto Trigger Mode

This mode is primarily intended for the DPD observation path. Upon enabling auto trigger mode, the ADS58J89 starts transmission of low resolution data. As soon as the L₁ counter is finished, the ADS58J89 immediately begins transmitting the high resolution output H₁. The HRES flag can also be embedded in the JESD204B output data stream. The counter values can be updated until a new burst mode cycles starts with transmission of low resolution samples. Any input on the trigger input pins is ignored.

See Figure 59 for an example of normal burst mode with automatic trigger:

Figure 59. Auto-Trigger Mode Duty Cycle Timing

7.4.6.7 TDD-Burst Mode

This mode is intended for the receive path in TDD LTE receivers. The individual counters for high and low resolution output data can be programmed so that the high resolution samples line up with receive (uplink) frames and the low resolution samples line up with transmit (downlink) and setup frames where no data is present in the receive path.

Table 10. TDD Burst Mode Duty Cycle

Option	Number of Setup Frames	Number of Downlink Frames	Number of Uplink Frames	Duty Cycle	High Resolution Output (500 MSPS)
1	1	8	1	1:9 (0.11)	14 bit
2		7	2	2:8 (0.25)	14 bit
3		6	3	3:7 (0.43)	12 bit
4		5	4	4:6 (0.67)	11/12 bit
5		1 to 4	5 to 8	(1+)	11 bit
6	2	6	2	2:8 (0.25)	14 bit
7		5	3	3:7 (0.43)	12 bit
8		4	4	4:6 (0.67)	11/12 bit
9		1 to 3	5 to 7	>1	11 bit

7.4.6.7.1 TDD Burst Mode Examples

Following are two examples to illustrate the intention for the TDD burst mode. The TDD frame has 10 equal size sub frames. For the downlink-uplink (DL-UL) configuration number 2 for example, the high and low resolution counters can be set for a given channel sampling rate to match the downlink-uplink profile as shown in Figure 60. The manual trigger is used to initiate the high resolution output data, which maintains synchronization. The counter L₁ covers the low resolution data across two consecutive TDD frames and most of setup frame.

For configuration number 2, a duty cycle of approximately 2 / 8 can be achieved; with a sampling rate of 500 MSPS, the high resolution output of 14 bit can be used.

Figure 60. TDD Burst Mode Example 1

For configuration number 3, a duty cycle of approximately 3 / 7 can be achieved and only two counters have to be programmed. With a sampling rate of 500 MSPS, a high resolution output of 12 bit can be used.

Figure 61. TDD Burst Mode Example 2

7.5.1 Serial Register Write

The internal register of the ADS58J89 can be programmed following these steps:

1. Drive SDENb pin low.
2. Set the R/W bit to ‘0’ (bit A7 of the 8 bit address).
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be written.
4. Write 16-bit data which is latched on the rising edge of SCLK.

Figure 62. Serial Register Write Timing Diagram

7.5.2 Serial Register Readout

The device includes a mode where the contents of the internal registers can be read back using the SDOUT and SDATA pins. This read-back mode may be useful as a diagnostic check to verify the serial interface communication between the external controller and the channel.

1. Drive SDENb pin low.
2. Set the RW bit (A7) to 1. This setting disables any further writes to the registers.
3. Initiate a serial interface cycle specifying the address of the register (A6 to A0) whose content has to be read.
4. The device outputs the contents (D15 to D0) of the selected register on the SDOUT/SDATA pin.
5. The external controller can latch the contents at the SCLK rising edge.
6. To enable register writes, reset the RW register bit to 0.

Figure 63. Serial Register Read Timing Diagram

7.6.1 Register Descriptions

7.6.1.2 Register Address 1

Figure 65. Register Address 1, Default 0xAF7A, Hex = 1

D15	D14	D13	D12	D11	D10	D9	D8	D7	D6	D5	D4	D3	D2	D1	D0
MODE 1	0	1	0	FOVR THRESH AB			FOVR LENGTH AB		FOVR THRESH CD			FOVR LENGTH CD		1	0

LEGEND: R/W = Read/Write; R = Read only; -n = value after reset

Table 14. Register Address 1 Field Descriptions

Bit	Field	Type	Reset	Description
D15	MODE 1			Set bit D15 to 0 for optimum performance
D13				Reads back 1
D11:D9	FOVR THRESH AB			Sets fast OVR thresholds for channel A and B The fast over-range detection is triggered 6 output clock cycles after the overload condition occurs. The threshold at which the OVR is triggered is: Input full scale × [decimal value of <over-range threshold>] / 8. After power-up or reset, the default value is 7 (decimal), which corresponds to an OVR threshold of 1.16-dB below full scale (20 × log(7/8)). Figure 66. OVR Detection Threshold
D8:D7	FOVR LENGTH AB			Determines minimum pulse length for FOVR output 00 = 1 clock cycle 01 = 2 clock cycles 10 = 4 clock cycles 11 = 8 clock cycles
D6:D4	FOVR THRESH CD			Sets fast OVR thresholds for channel C and D See description for channel A and B
D3:D2	FOVR LENGTH CD			Determines minimum pulse length for FOVR output 00 = 1 clock cycle 01 = 2 clock cycles 10 = 4 clock cycles 11 = 8 clock cycles
D1				Reads back 1