JAJSEQ8D May   2013  – March 2018 ADS7250 , ADS7850 , ADS8350

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Devices
    6. 6.6  Electrical Characteristics: ADS7250
    7. 6.7  Electrical Characteristics: ADS7850
    8. 6.8  Electrical Characteristics: ADS8350
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics: ADS7250
    12. 6.12 Typical Characteristics: ADS7850
    13. 6.13 Typical Characteristics: ADS8350
    14. 6.14 Typical Characteristics: All Devices
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Input
        1. 7.3.2.1 Analog Input Full-Scale Range
      3. 7.3.3 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
      2. 7.4.2 Short-Cycling, Frame Abort, and Reconversion Feature
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at 750-kSPS Throughput
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ADC Reference Driver
          2. 8.2.1.2.2 ADC Input Driver
            1. 8.2.1.2.2.1 Input Amplifier Selection
            2. 8.2.1.2.2.2 Antialiasing Filter
        3. 8.2.1.3 Application Curve
      2. 8.2.2 DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at 750-kSPS Throughput
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 ADC Reference Driver
          2. 8.2.2.2.2 ADC Input Driver
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics: All Devices

minimum and maximum specifications are at TA = –40°C to 125°C, AVDD = 5 V, VREFIN_A = VREFIN_B = VREF, and tDATA = 750 kSPS (unless otherwise noted); typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR Full-scale input range,
(AINP_x – AINM_x)		 AVDD ≥ 2 x VREF(1),
AINM_x = VREF 		–VREF VREF V
VINP Absolute input voltage,
(AINP_x to REFGND)		 AVDD ≥ 2 x VREF(1),
AINM_x = VREF 		0 2 × VREF V
VINM Absolute input voltage,
(AINM_x to REFGND)		 VREF – 0.1 VREF VREF + 0.1 V
CIN Input capacitance In sample mode 40 pF
In hold mode 4
IIN Input leakage current 1.5 nA
SAMPLING DYNAMICS
fDATA Data rate 750 kSPS
tA Aperture delay 8 ns
tA match ADC_A to ADC_B 40 ps
Aperture jitter 10 ps
fCLK Clock frequency 24 MHz
VOLTAGE REFERENCE INPUT
VREF Reference input voltage 2.25 2.5 AVDD / 2(1) V
IREF Reference input current 300 µA
Reference leakage current 1 µA
CREF External ceramic reference capacitance 10 µF
DIGITAL INPUTS(2)
VIH Input voltage, high 0.7 DVDD DVDD + 0.3 V
VIL Input voltage, low –0.3 0.3 DVDD V
DIGITAL OUTPUTS(2)
VOH Output voltage, high IOH = 500-µA source 0.8 DVDD DVDD V
VOL Output voltage, low IOH = 500-µA sink 0 0.2 DVDD V
POWER SUPPLY
AVDD Analog supply voltage,
AVDD to GND		 4.5(1) 5.0 5.5 V
DVDD Digital supply voltage,
DVDD to GND		 1.65 5.5 V
IA-DYNA Analog supply current,
during conversion		 AVDD = 5 V, throughput = max 8 9 mA
IA-STAT Analog supply current,
no conversion		 AVDD = 5 V, static 5 7 mA
IDVDD Digital supply current DVDD = 3.3 V 0.25 mA
PD-DYNA Power dissipation AVDD = 5 V, throughput = max 40 45 mW
PD-STAT AVDD = 5 V, static 25 35
(1) The AVDD supply voltage defines the permissible voltage swing on the analog input pins. To use the maximum dynamic range of the analog input pins, VREFIN_x and AVDD must be in the respective permissible range with AVDD ≥ 2 x VREFIN_x.
(2) Specified by design; not production tested.