JAJSEQ8D May   2013  – March 2018 ADS7250 , ADS7850 , ADS8350

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     機能ブロック図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Devices
    6. 6.6  Electrical Characteristics: ADS7250
    7. 6.7  Electrical Characteristics: ADS7850
    8. 6.8  Electrical Characteristics: ADS8350
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics: ADS7250
    12. 6.12 Typical Characteristics: ADS7850
    13. 6.13 Typical Characteristics: ADS8350
    14. 6.14 Typical Characteristics: All Devices
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Input
        1. 7.3.2.1 Analog Input Full-Scale Range
      3. 7.3.3 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
      2. 7.4.2 Short-Cycling, Frame Abort, and Reconversion Feature
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at 750-kSPS Throughput
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ADC Reference Driver
          2. 8.2.1.2.2 ADC Input Driver
            1. 8.2.1.2.2.1 Input Amplifier Selection
            2. 8.2.1.2.2.2 Antialiasing Filter
        3. 8.2.1.3 Application Curve
      2. 8.2.2 DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at 750-kSPS Throughput
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 ADC Reference Driver
          2. 8.2.2.2.2 ADC Input Driver
        3. 8.2.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.2 Short-Cycling, Frame Abort, and Reconversion Feature

Referring to Table 2, the ADS8350 requires a minimum of 31 SCLK falling edges between the beginning and end of the frame to complete the 16-bit data transfer, the ADS7850 requires a minimum of 29 SCLK falling edges between the beginning and end of the frame to complete the 14-bit data transfer, and the ADS7250 requires a minimum of 27 SCLK falling edges between the beginning and end of the frame to complete the 12-bit data transfer. However, CS can be brought high at any time during the frame to abort the frame or to short-cycle the converter.

As shown in Figure 53, if CS is brought high before the 15th SCLK falling edge, the device aborts the conversion and starts sampling the new analog input signal.

ADS8350 ADS7850 ADS7250 tim_conv_feature1_bas580.gifFigure 53. Frame Aborted before 15th SCLK Falling Edge

If CS is brought high after the 15th SCLK falling edge (as shown in Figure 54), the output data bits latched into the digital host before this CS rising edge are still valid data corresponding to sample N.

ADS8350 ADS7850 ADS7250 tim_conv_feature2_bas580.gifFigure 54. Frame Aborted after 15th SCLK Falling Edge

After aborting the current frame, CS must be kept high for tPH_CS_SHRT to ensure that the minimum acquisition time (tACQ) is provided for the next conversion.