The ADS8363 is a dual, 16-bit, 1-MSPS analog-to-digital converter (ADC) with eight pseudo- or four fully-differential input channels grouped into two pairs for simultaneous signal acquisition. The analog inputs are maintained differentially to the input of the ADC. The input multiplexer can be used in either pseudo-differential mode, supporting up to four channels per ADC (4x2), or in fully-differential mode that allows to convert up to two inputs per ADC (2x2). The ADS7263 is a 14-bit version and the ADS7223 is a 12-bit version of the ADS8363.
The ADS8363, ADS7263, and ADS7223 offer two programmable reference outputs, flexible supply voltage ranges, a programmable auto-sequencer, data storage of up to four conversion results per channel, and several power-down features.
All devices are offered in a 5-mm x 5-mm, 32-pin VQFN package.
PART NUMBER | PACKAGE | BODY SIZE (NOM) |
---|---|---|
ADSxxx3 | VQFN (32) | 5.00 mm x 5.00 mm |
Changes from C Revision (January 2017) to D Revision
Changes from B Revision (January 2011) to C Revision
Changes from A Revision (December, 2010) to B Revision
Changes from * Revision (October, 2010) to A Revision
PRODUCT | RESOLUTION | NMC | INL | SNR | THD |
---|---|---|---|---|---|
ADS8363 | 16 bits | 16 or 15 bits(1) | ±3 or ±4 LSB(1) | 93 dB (typ) | –98 dB (typ) |
ADS7263 | 14 bits | 14 bits | ±1 LSB | 85 dB (typ) | –92 dB (typ) |
ADS7223 | 12 bits | 12 bits | ±0.5 LSB | 73 dB (typ) | –86 dB (typ) |
PIN | TYPE(1) | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
AGND | 12, 30 | P | Analog ground. Connect to analog ground plane. |
AVDD | 13, 29 | P | Analog power supply, 2.7 V to 5.5 V. Decouple to AGND with a 1-μF ceramic capacitor. |
BUSY | 23 | DO | Converter busy indicator. BUSY goes high when the inputs are in hold mode and returns to low after the conversion is complete. |
CHA0N/CHA0 | 8 | AI | Fully-differential inverting analog input channel A1 or pseudo-differential input A0 |
CHA0P/CHA1 | 7 | AI | Fully-differential noninverting analog input channel A1 or pseudo-differential input A1 |
CHA1N/CHA2 | 6 | AI | Fully-differential inverting analog input channel A1 or pseudo-differential input A2 |
CHA1P/CHA3 | 5 | AI | Fully-differential noninverting analog input channel A1 or pseudo-differential input A3 |
CHB0N/CHB0 | 4 | AI | Fully-differential inverting analog input channel B0 or pseudo-differential input B0 |
CHB0P/CHB1 | 3 | AI | Fully-differential noninverting analog input channel B0 or pseudo-differential input B1 |
CHB1N/CHB2 | 2 | AI | Fully-differential inverting analog input channel B1 or pseudo-differential input B2 |
CHB1P/CHB3 | 1 | AI | Fully-differential noninverting analog input channel B1 or pseudo-differential input B3 |
CLOCK | 22 | DI | External clock input. The range is 0.5 MHz to 20 MHz in half-clock mode, or 1 MHz to 40 MHz in full-clock mode. |
CMA | 31 | AI | Common-mode voltage input for channels Ax (in pseudo-differential mode only). |
CMB | 32 | AI | Common-mode voltage input for channels Bx (in pseudo-differential mode only). |
CONVST | 19 | DI | Conversion start. The ADC switches from sample into hold mode on the rising edge of CONVST. Thereafter, the conversion starts with the next rising edge of the CLOCK pin. |
CS | 21 | DI | Chip select. When this pin is low, the SDOx, SDI, and RD pins are active; when this pin is high, the SDOx outputs are 3-stated, and the SDI and RD inputs are ignored. |
DGND | 28 | P | Digital ground. Connect to digital ground plane. |
DVDD | 27 | P | Digital supply, 2.3 V to 5.5 V. Decouple to DGND with a 1-μF ceramic capacitor. |
M0 | 17 | DI | Mode pin 0. Selects analog input channel mode (see Table 5). |
M1 | 16 | DI | Mode pin 1. Selects the digital output mode (see Table 5). |
NC | 14, 15, 26 | NC | This pin is not internally connected. |
RD | 20 | DI | Read data. Synchronization pulse for the SDOx outputs and SDI input. RD only triggers when CS is low. |
REFIO1 | 9 | AIO | Reference voltage input/output 1. A ceramic capacitor of 22 µF connected to RGND is required. |
REFIO2 | 10 | AIO | Reference voltage input/output 2. A ceramic capacitor of 22 µF connected to RGND is required. |
RGND | 11 | P | Reference ground. Connect to analog ground plane with a dedicated via. |
SDI | 18 | DI | Serial data input. This pin is used to set up of the internal registers, and can also be used in ADS8361-compatible manner. The data on SDI are ignored when CS is high. |
SDOA | 25 | DO | Serial data output for converter A. 3-state when CS is high. |
SDOB | 24 | DO | Serial data output for converter B. Active only if M1 is low. 3-state when CS is high. |