JAJSEQ8D May   2013  – March 2018 ADS7250 , ADS7850 , ADS8350

PRODUCTION DATA.  

  1. 特長
  2. アプリケーション
  3. 概要
    1.     機能ブロック図
  4. 改訂履歴
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: All Devices
    6. 6.6  Electrical Characteristics: ADS7250
    7. 6.7  Electrical Characteristics: ADS7850
    8. 6.8  Electrical Characteristics: ADS8350
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics: ADS7250
    12. 6.12 Typical Characteristics: ADS7850
    13. 6.13 Typical Characteristics: ADS8350
    14. 6.14 Typical Characteristics: All Devices
  7. Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference
      2. 7.3.2 Analog Input
        1. 7.3.2.1 Analog Input Full-Scale Range
      3. 7.3.3 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Serial Interface
      2. 7.4.2 Short-Cycling, Frame Abort, and Reconversion Feature
  8. Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 DAQ Circuit: Maximum SINAD for a 10-kHz Input Signal at 750-kSPS Throughput
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 ADC Reference Driver
          2. 8.2.1.2.2 ADC Input Driver
            1. 8.2.1.2.2.1 Input Amplifier Selection
            2. 8.2.1.2.2.2 Antialiasing Filter
        3. 8.2.1.3 Application Curve
      2. 8.2.2 DAQ Circuit: Maximum SINAD for a 100-kHz Input Signal at 750-kSPS Throughput
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
          1. 8.2.2.2.1 ADC Reference Driver
          2. 8.2.2.2.2 ADC Input Driver
        3. 8.2.2.3 Application Curve
  9. Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ(パッケージ|ピン)
サーマルパッド・メカニカル・データ
発注情報

Antialiasing Filter

Converting analog-to-digital signals requires sampling an input signal at a constant rate. Any higher frequency content in the input signal beyond half the sampling frequency is digitized and folded back into the low-frequency spectrum. This process is called aliasing. Therefore, an analog, antialiasing filter must be used to remove the harmonic content from the input signal before being sampled by the ADC. An antialiasing filter is designed as a low-pass, RC filter, for which the 3-dB bandwidth is optimized based on specific application requirements. For dc signals with fast transients (including multiplexed input signals), a high-bandwidth filter is designed to allow accurately settling the signal at the ADC inputs during the small acquisition time window. For ac signals, the filter bandwidth should be kept low to band-limit the noise fed into the ADC input, thereby increasing the signal-to-noise ratio (SNR) of the system.

Besides filtering noise from the front-end drive circuitry, the RC filter also helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected across the ADC inputs (as shown in Figure 57).

ADS8350 ADS7850 ADS7250 apps_aaf_8350.gifFigure 57. Antialiasing Filter

This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. As a rule of thumb, the value of this capacitor should be at least 10 times the specified value of the ADC sampling capacitance. For these devices, the input sampling capacitance is equal to 40 pF. Thus, the value of CFLT should be greater than 400 pF. The capacitor should be a COG- or NPO-type because these capacitor types have a high-Q, low-temperature coefficient, and stable electrical characteristics under varying voltages, frequency, and time.

Note that driving capacitive loads can degrade the phase margin of the input amplifiers, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT is helpful from the amplifier stability perspective, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability and distortion of the design. For these devices, TI recommends limiting the value of RFLT to a maximum of 22 Ω in order to avoid any significant degradation in linearity performance. The tolerance of the selected resistors can be chosen as 1% because the use of a differential capacitor at the input balances the effects resulting from any resistor mismatch.

The input amplifier bandwidth should be much higher than the cutoff frequency of the antialiasing filter. TI strongly recommends performing a SPICE simulation to confirm that the amplifier has more than 40° phase margin with the selected filter. Simulation is critical because even with high-bandwidth amplifiers, some amplifiers might require more bandwidth than others to drive similar filters. If an amplifier has less than a 40° phase margin with 22-Ω resistors, using a different amplifier with higher bandwidth or reducing the filter cutoff frequency with a larger differential capacitor is advisable.

The application circuit shown in Figure 56 is optimized to achieve lowest distortion and lowest noise for a 10-kHz input signal. The input signal is processed through a high-bandwidth, low-distortion amplifier in an inverting gain configuration and a low-pass RC filter before being fed into the ADS8350 operating at 750-kSPS throughput.

As a rule of thumb, the distortion from the input driver should be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the amplifier in an inverting gain configuration that establishes a fixed common-mode level for the circuit. The low-power OPA836, used as an input driver, provides exceptional ac performance because of its extremely low-distortion, high-bandwidth specifications. In addition, the components of the antialiasing filter are such that the noise from the front-end circuit is kept low without adding distortion to the input signal.

NOTE

The same circuit can be used with the ADS7250 and ADS7850 to achieve their rated specifications.