JAJS503C June   2008  – July 2018 ADS7950 , ADS7951 , ADS7952 , ADS7953 , ADS7954 , ADS7955 , ADS7956 , ADS7957 , ADS7958 , ADS7959 , ADS7960 , ADS7961

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     詳細ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TSSOP Packages
    2.     Pin Functions: VQFN Packages
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TSSOP
    5. 7.5  Thermal Information: VQFN
    6. 7.6  Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953
    7. 7.7  Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957
    8. 7.8  Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics (All ADS79xx Family Devices)
    11. 7.11 Typical Characteristics (12-Bit Devices Only)
    12. 7.12 Typical Characteristics (12-Bit Devices Only)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Power Saving
    4. 8.4 Device Functional Modes
      1. 8.4.1 Channel Sequencing Modes
      2. 8.4.2 Device Programming and Mode Control
        1. 8.4.2.1 Mode Control Register
        2. 8.4.2.2 Program Registers
      3. 8.4.3 Device Power-Up Sequence
      4. 8.4.4 Operating in Manual Mode
      5. 8.4.5 Operating in Auto-1 Mode
      6. 8.4.6 Operating in Auto-2 Mode
      7. 8.4.7 Continued Operation in a Selected Mode
    5. 8.5 Programming
      1. 8.5.1 Digital Output
      2. 8.5.2 GPIO Registers
      3. 8.5.3 Alarm Thresholds for GPIO Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
    2. 9.2 Typical Applications
      1. 9.2.1 Unbuffered Multiplexer Output (MXO)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 OPA192 Buffered Multiplexer Output (MXO)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
  • DBT|30
サーマルパッド・メカニカル・データ
発注情報

8.5.1 Digital Output

As discussed previously in Overview, the digital output of the ADS79xx devices is SPI compatible. The following tables list the output codes corresponding to various analog input voltages.

Table 8. Ideal Input Voltages for 12-Bit Devices and Output Codes for 12-Bit Devices (ADS7950/51/52/53)

DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full scale range Range 1 → VREF Range 2 → 2×VREF STRAIGHT BINARY
Least significant bit (LSB) VREF / 4096 2VREF / 4096 BINARY CODE HEX CODE
Full scale VREF – 1 LSB 2VREF – 1 LSB 1111 1111 1111 FFF
Midscale VREF / 2 VREF 1000 0000 0000 800
Midscale – 1 LSB VREF / 2 – 1 LSB VREF – 1 LSB 0111 1111 1111 7FF
Zero 0 V 0 V 0000 0000 0000 000

Table 9. Ideal Input Voltages for 10-Bit Devices and Digital Output Codes for 10-Bit Devices (ADS7954/55/56/57)

DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full scale range Range 1 → VREF Range 2 → 2×VREF STRAIGHT BINARY
Least significant bit (LSB) VREF / 1024 2VREF / 1024 BINARY CODE HEX CODE
Full scale VREF – 1 LSB 2VREF – 1 LSB 0011 1111 1111 3FF
Midscale VREF / 2 VREF 0010 0000 0000 200
Midscale – 1 LSB VREF / 2 – 1 LSB VREF – 1 LSB 0001 1111 1111 1FF
Zero 0 V 0 V 0000 0000 0000 000

Table 10. Ideal Input Voltages for 8-Bit Devices and Digital Output Codes for 8-Bit Devices (ADS7958/59/60/61)

DESCRIPTION ANALOG VALUE DIGITAL OUTPUT
Full scale range Range 1 → VREF Range 2 → 2×VREF STRAIGHT BINARY
Least significant bit (LSB) VREF / 256 2VREF / 256 BINARY CODE HEX CODE
Full scale VREF – 1 LSB 2VREF – 1 LSB 1111 1111 FF
Midscale VREF / 2 VREF 1000 0000 80
Midscale – 1 LSB VREF / 2 – 1 LSB VREF – 1 LSB 0111 1111 7F
Zero 0 V 0 V 0000 0000 00