JAJS503C June   2008  – July 2018 ADS7950 , ADS7951 , ADS7952 , ADS7953 , ADS7954 , ADS7955 , ADS7956 , ADS7957 , ADS7958 , ADS7959 , ADS7960 , ADS7961

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     詳細ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TSSOP Packages
    2.     Pin Functions: VQFN Packages
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TSSOP
    5. 7.5  Thermal Information: VQFN
    6. 7.6  Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953
    7. 7.7  Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957
    8. 7.8  Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics (All ADS79xx Family Devices)
    11. 7.11 Typical Characteristics (12-Bit Devices Only)
    12. 7.12 Typical Characteristics (12-Bit Devices Only)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Power Saving
    4. 8.4 Device Functional Modes
      1. 8.4.1 Channel Sequencing Modes
      2. 8.4.2 Device Programming and Mode Control
        1. 8.4.2.1 Mode Control Register
        2. 8.4.2.2 Program Registers
      3. 8.4.3 Device Power-Up Sequence
      4. 8.4.4 Operating in Manual Mode
      5. 8.4.5 Operating in Auto-1 Mode
      6. 8.4.6 Operating in Auto-2 Mode
      7. 8.4.7 Continued Operation in a Selected Mode
    5. 8.5 Programming
      1. 8.5.1 Digital Output
      2. 8.5.2 GPIO Registers
      3. 8.5.3 Alarm Thresholds for GPIO Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
    2. 9.2 Typical Applications
      1. 9.2.1 Unbuffered Multiplexer Output (MXO)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 OPA192 Buffered Multiplexer Output (MXO)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RGE|24
  • DBT|30
サーマルパッド・メカニカル・データ
発注情報

8.4.5 Operating in Auto-1 Mode

Figure 52 illustrates the steps involved in entering and operating in Auto-1 Channel Sequencing mode. Table 2 lists the Mode Control Register settings for Auto-1 mode.

ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 man2_mode_las605.gifFigure 52. Entering and Running in Auto-1 Channel Sequencing Mode

Consider a case where Auto-1 mode is selected to scan channels 2 (CH2), 5 (CH5), and 6 (CH6) as represented in Figure 53. The program register for Auto-1 mode must be programmed as described in Figure 53 before entering into this auto sequencing mode. The device enters into Auto-1 mode on receiving the Auto-1 mode command in the Nth frame. This step causes the device to find the first enabled channel in ascending order and switch the MUX for CH2 in the (N+1)th frame. In the (N+2)th frame, the ADC samples the signal on CH2, shifts out the conversion results, and the MUX also internally switches to CH5. In the (N+3)th frame, the ADC samples and shifts out the conversion result for CH5 and the MUX also internally switches to CH6. This process repeats until the last enabled channel is reached, in which case the process loops back to the first enabled channel. Entering Auto-1 mode from any other mode also causes the device to restart from the first enabled channel. However, modifying the contents of the Auto-1 mode program register while operating in Auto-1 mode causes the device to scan for the next enabled channel.

ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 AUTO1_SLAS605C.gifFigure 53. Example Auto-1 Mode Timing Diagram

Table 2. Mode Control Register Settings for Auto-1 Mode

BITS RESET STATE LOGIC STATE FUNCTION
DI15-12 0001 0010 Selects Auto-1 Mode
DI11 0 1 Enables programming of bits DI10-00.
0 Device retains values of DI10-00 from previous frame.
DI10 0 1 The channel counter is reset to the lowest programmed channel in the Auto-1 Program Register
0 The channel counter increments every conversion (No reset)
DI09-07 000 xxx Do not care
DI06 0 0 Selects 0 to VREF input range (Range 1)
1 Selects 0 to 2xVREF input range (Range 2)
DI05 0 0 Device normal operation (no powerdown)
1 Device powers down on the 16th SCLK falling edge
DI04 0 0 SDO outputs current channel address of the channel on DO15..12 followed by 12-bit conversion result on DO11..00.
1 GPIO3-GPIO0 data (both input and output) is mapped onto DO15-DO12 in the order shown below. Lower data bits DO11-DO00 represent 12-bit conversion result of the current channel.
DO15 DO14 DO13 DO12
GPIO3(1) GPIO2(1) GPIO1(1) GPIO0(1)
DI03-00 0000 GPIO data for the channels configured as output. Device will ignore the data for the channel which is configured as input. SDI bit and corresponding GPIO information is given below
DI03 DI02 DI01 DI00
GPIO3(1) GPIO2(1) GPIO1(1) GPIO0(1)
(1) GPIO 1 to 3 are available only in TSSOP packaged devices. QFN device offers GPIO 0 only.

The Auto-1 Program Register is programmed (once on powerup or reset) to pre-select the channels for the Auto-1 sequence. Auto-1 Program Register programming requires two CS frames for complete programming. In the first CS frame the device enters the Auto-1 register programming sequence and in the second frame it programs the Auto-1 Program Register. Refer to Table 2, Table 3, and Table 4 for complete details.

ADS7950 ADS7951 ADS7952 ADS7953 ADS7954 ADS7955 ADS7956 ADS7957 ADS7958 ADS7959 ADS7960 ADS7961 auto_reg_fc_las605.gif

NOTE:

The device continues its operation in selected mode during programming. SDO is valid, however it is not possible to change the range or write GPIO data into the device during programming.
Figure 54. Auto-1 Register Programming Flowchart

Table 3. Program Register Settings for Auto-1 Mode

BITS RESET STATE LOGIC STATE FUNCTION
FRAME 1
DI15-12 NA 1000 Device enters Auto-1 program sequence. Device programming is done in the next frame.
DI11-00 NA Do not care
FRAME 2
DI15-00 All 1s 1 (individual bit) A particular channel is programmed to be selected in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; for example,
DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00
0 (individual bit) A particular channel is programmed to be skipped in the channel scanning sequence. The channel numbers are mapped one-to-one with respect to the SDI bits; for example
DI15 → Ch15, DI14 → Ch14 … DI00 → Ch00

Table 4. Mapping of Channels to SDI Bits for 16, 12, 8, 4 Channel Devices

Device(1) SDI BITS
DI15 DI14 DI13 DI12 DI11 DI10 DI09 DI08 DI07 DI06 DI05 DI04 DI03 DI02 DI01 DI00
16 Chan 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
12 Chan X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
8 Chan X X X X X X X X 1/0 1/0 1/0 1/0 1/0 1/0 1/0 1/0
4 Chan X X X X X X X X X X X X 1/0 1/0 1/0 1/0
(1) When operating in Auto-1 mode, the device only scans the channels programmed to be selected.