8.3.1 Device Operation

Figure 45, Figure 46, Figure 47, and Figure 48 illustrate device operation timing. Device operation is controlled with the CS, SCLK, and SDI pins. The device outputs data on the SDO pin.

Figure 45. Device Operation Timing Diagram

Each frame begins with the falling edge of the CS pin. With the falling edge of the CS pin, the input signal from the selected channel is sampled, and the conversion process is initiated. The device outputs data while the conversion is in progress. The 16-bit data word contains a 4-bit channel address, followed by a 12-bit conversion result in most-significant-bit (MSB) first format. The GPIO status can be read instead of the channel address (see Table 1, Table 2, and Table 5).

The device selects a new multiplexer channel on the second SCLK falling edge. The acquisition phase begins on the 14th SCLK rising edge. On the next CS falling edge the acquisition phase ends, and the device starts a new frame.

There are four general-purpose IO (GPIO) pins. These pins can be individually programmed as GPO or GPI. Using these pins for preassigned functions is also possible (see Table 11). GPO data can be written into the device through the SDI line. The device refreshes the GPO data on the CS falling edge according to the SDI data written in previous frame.

Similarly the device latches the GPI status on the CS falling edge and outputs the GPI data on the SDO line (if GPI read is enabled by writing DI04 = 1 in the previous frame) in the same frame starting with the CS falling edge.

Figure 46. Serial Interface Timing Diagram for 8-Bit Devices
(ADS7958, ADS7959, ADS7960, and ADS7961)

Figure 47. Serial Interface Timing Diagram for 10-Bit Devices (ADS7954, ADS7956, and ADS7957)

Figure 48. Serial Interface Timing Diagram for 12-Bit Devices
(ADS7950, ADS7951, ADS7952, and ADS7953)

The falling edge of the CS pin clocks out the DO-15 bit (the first bit of the four bit channel address), and remaining address bits are clocked out on every falling edge of SCLK until the third falling edge. The conversion result MSB is clocked out on the fourth SCLK falling edge and LSB on the 11th, 13th, or 15th falling edge respectively for 8-bit, 10-bit, or 12-bit devices. On the 16th falling edge of the SCLK pin, the SDO pin enters tri-state condition. The conversion ends on the 16th falling edge of SCLK.

While the device outputs data on the SDO pin, a 16-bit word is read on the SDI pin. The SDI data are latched on every rising edge of the SCLK pin beginning with the first clock; see Figure 46, Figure 47, and Figure 48.

The CS pin can be asserted (pulled high) only after 16 clocks have elapsed.

The device has two (high and low) programmable alarm thresholds per channel. If the input crosses these limits the device flags out an alarm on the GPIO0 or GPIO1 pin depending on the GPIO-program register settings (see Table 11). The alarm is asserted (under the alarm conditions) on the 12th falling edge of the SCLK pin in the same frame when a data conversion is in progress. The alarm output is reset on the tenth falling edge of the SCLK pin in the next frame.

8.3.2 Device Power-up Sequence

Figure 49 illustrates the device power-up sequence. Manual mode is the default power-up channel-sequencing mode and channel-0 is the first channel by default. As explained previously, these devices offer program registers to configure user-programmable features (such as GPIO, alarm, and to preprogram the channel sequence for the auto modes). At power up or on reset, these registers are set to the default values listed in Table 1 to Table 11. Program these registers on power up or after reset. When configured, the device is ready to use in any of the three channel sequencing modes: manual, auto-1, and auto-2.

A. The device continues operation in manual-mode channel 0 throughout the programming sequence and outputs valid conversion results. Changing the channel, range, or GPIO is possible by inserting extra frames in between two programming blocks. Bypassing any programming block is also possible if that feature in not intended for use.

B. Reprogramming the device at any time during operation, regardless of what mode the device is in, is possible. During programming, the device continues operation in whatever mode it is in and outputs valid data.

Figure 49. Device Power-Up Sequence

8.3.3 Analog Input

The ADS79x-Q1 device family offers 8-bit, 10-bit, and 12-bit ADCs with 4-channel, 8-channel, 12-channel, 16-channel multiplexers for analog input. The multiplexer output is available on the MXO pin. The AINP pin is the ADC input pin. The devices offers flexibility for a system designer as both MXO and AINP are accessible externally.

Figure 50 shows the equivalent circuit at the input and output of the multiplexer and the input of the converter during sampling. When the converter enters hold mode, the input impedance at AINP is greater than 1 GΩ.

Figure 50. ADC and MUX Equivalent Circuit

When the converter samples an input, the voltage difference between the AINP and AGND pins is captured on the internal capacitor array. The peak input current through the analog inputs depends upon a number of factors including sample rate, input voltage, and source impedance. The current into the ADS79xx-Q1 device charges the internal capacitor array during the sample period. After this capacitance is fully charged, there is no further input current.

To maintain the linearity of the converter, the Ch0 through Chn and AINP inputs must be within the input range limits specified. Outside of these ranges, converter linearity may not meet specifications.

8.3.4 Reference

The ADS79xx-Q1 device can operate with an external 2.5-V ±10-mV reference. A clean, low-noise, well-decoupled reference voltage on the REF pin is required to ensure good performance from the converter. A low-noise, band-gap reference (such as the REF5025 device) can be used to drive this pin. A 10-μF ceramic decoupling capacitor is required between the REF and GND pins of the converter. Place the capacitor as close as possible to the device pins.

8.3.5 Power Saving

The ADS79xx-Q1 device offers a power-down feature to save power when not in use. There are two ways to power down the device. The device can be powered down by writing the DI05 bit equal to 1 in the mode control register (see Table 1, Table 2, and Table 5). In this case, the device powers down on the 16th falling edge of the SCLK pin in the next data frame. Another way to power down the device is through the GPIO pins. The GPIO3 pin can act as a PD input (see Table 11 for assigning this functionality to the GPIO3 pin) which is an asynchronous and active-low input. The device powers down instantaneously after the GPIO3 pin (PD) equals 0. The device powers up again on the CS falling edge when the DI05 bit equals 0 in the mode control register, and the GPIO3 pin (PD) equals 1.

8.4.1 Channel Sequencing Modes

There are three modes for channel sequencing, including manual mode, auto-1 mode, and auto-2 mode. Mode selection occurs by writing into the control register (see Table 1, Table 2, and Table 5). A new multiplexer channel is selected on the second falling edge of SCLK (as shown in Figure 45) in all three modes.

When programmed, the device retains the program register settings until the device is powered down, reset, or reprogrammed. The device is allowed to exit and reenter the auto-1 mode any number of times without disturbing the program register settings.

The auto-1 program register is reset to F, FF, FFF, or FFFF (hex) for the 4-channel, 8-channel, 12-channel, or 16-channel devices, respectively, upon device power up or reset (implying the device scans all channels in ascending order).

When programmed, the device retains the program register settings until the device is powered down, reset, or reprogrammed. The device is allowed to exit and re-enter auto-2 mode any number of times, without disturbing the program register settings.

On power up or reset, bits D9 to D6 of the auto-2 program register are reset to 3, 7, B, or F (hex) 4-channel, 8-channel, 12-channel or 16-channel devices, respectively (implying the device scans all channels in ascending order).

8.4.2 Device Programming and Mode Control

The following sections describe device programming and mode control. The ADS79xx-Q1 device feature two types of registers to configure and operate the devices in different modes. These registers are referred as configuration registers. The two types of configuration registers are mode control registers and program registers.

8.4.3 Operating In Manual Mode

Figure 51 illustrates details regarding entering and running in manual channel-sequencing mode. Table 1 lists the mode control register settings for manual mode in detail. Note that there are no program registers for manual mode.

Figure 51. Entering and Running in Manual Channel-Sequencing Mode

8.4.4 Operating In Auto-1 Mode

Figure 52 shows a flowchart containing the details regarding entering and running in auto-1 channel-sequencing mode. Table 2 lists the mode control register settings for auto-1 mode in detail.

Figure 52. Entering and Running in Auto-1 Channel-Sequencing Mode

The auto-1 program register is programmed (once on power up or reset) to preselect the channels for the auto-1 sequence, as shown in Figure 53. The auto-1 program-register programming requires two CS frames for complete programming. In the first CS frame, the device enters the auto-1 register programming sequence, and in the second frame the device programs the auto-1 program register. For complete details see Table 2, Table 3, and Table 4.

A. Per Table 3 and Table 4.

B. The device continues operation in the selected mode during programming. The SDO pin is valid, however changing the range or writing the GPIO data into the device during programming is not possible.

Figure 53. Auto-1 Register Programming Flowchart

8.4.5 Operating In Auto-2 Mode

Figure 54 illustrates the details regarding entering and running in auto-2 channel-sequencing mode. Table 5 lists the mode-control register settings for auto-2 mode in detail.

Figure 54. Entering and Running in Auto-2 Channel-Sequencing Mode

The auto-2 program register is programmed (once on power up or reset) to preselect the last channel (or sequence depth) in the auto-2 sequence. Unlike auto-1 program-register programming, auto-2 program-register programming requires only one CS frame for complete programming. Figure 55 and Table 6 provide complete details.

A. See Table 6.

B. The device continues operation in the selected mode during programming. The SDO pin is valid, however changing the range or writing the GPIO data into the device during programming is not possible.

Figure 55. Auto-2 Register Programming Flowchart

8.4.6 Continued Operation In A Selected Mode

When a device is programmed to operate in one of the modes, the user can continue to operate in the same mode. Table 7 lists mode-control register settings to continue operating in a selected mode.

Table 8. Ideal Input Voltages and Output Codes for 8-Bit Devices
(ADS7958, ADS7959, ADS7960, and ADS7961)

Table 9. Ideal Input Voltages and Output Codes for 10-Bit Devices
(ADS7958, ADS7959, ADS7960, and ADS7961)

Table 10. Ideal Input Voltages and Output Codes for 12-Bit Devices
(ADS7950, ADS7951, ADS7952, and ADS7953)

8.6.1 GPIO Registers

The device has four general-purpose input and output (GPIO) pins. Each of the four pins can be independently programmed as general purpose output (GPO) or general purpose input (GPI). Using the GPIOs pins for some preassigned functions (see Table 11) is possible. The GPO data can be written into the device through the SDI line. The device refreshes the GPO data on every CS falling edge as per the SDI data written in the previous frame. Similarly, the device latches the GPI status on the CS falling edge and outputs it on the SDO pin (if the GPI pin is read-enabled by writing bit DI04 equal to 1 during the previous frame) in the same frame starting on the CS falling edge.

Figure 56 shows the details regarding programming the GPIO registers. Table 11 lists the details regarding GPIO-register programming settings.

A. See Table 12 for DI11 to DI00 data.

B. The device continues its operation in selected mode during programming. SDO is valid, however changing the range or writing GPIO data into the device during programming is not possible.

Figure 56. GPIO Program-Register Programming Flowchart

8.6.2 Alarm Thresholds for GPIO Pins

Each channel has two alarm program registers, one for setting the high alarm threshold and the other for setting the low alarm threshold. For ease of programming, two alarm programming registers per channel, corresponding to four consecutive channels, are assembled into one group (a total of eight registers). There are four of these groups for 16-channel devices, and one, two or three of these groups for the 12-, 8-, or 4-channel devices, respectively. Table 12 lists the grouping of the various channels for each device in the ADS79xx-Q1 family. Figure 57 illustrates the details regarding programming the alarm thresholds. Table 13 lists the details regarding the alarm-program register settings.

Each alarm group requires nine CS frames for programming the respective alarm thresholds. In the first frame the device enters the programming sequence and in each subsequent frame the device programs one of the registers from the group. The device offers a feature to program less than eight registers in one programming sequence. The device exits the alarm threshold programming sequence in the next frame after encountering the first exit alarm program bit high.

A. xx indicates a group of four channels (see Table 12).

B. Per Table 12.

C. The device continues operation in the selected mode during programming. The SDO pin is valid, however changing the range or writing the GPIO data into the device during programming is not possible.

Figure 57. Alarm Program Register Programming Flowchart