JAJS503C June   2008  – July 2018 ADS7950 , ADS7951 , ADS7952 , ADS7953 , ADS7954 , ADS7955 , ADS7956 , ADS7957 , ADS7958 , ADS7959 , ADS7960 , ADS7961

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
    1.     詳細ブロック図
  3. 3 概要
  4. 4 改訂履歴
  5. 5 デバイス比較表
  6. 6 Pin Configuration and Functions
    1.     Pin Functions: TSSOP Packages
    2.     Pin Functions: VQFN Packages
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information: TSSOP
    5. 7.5  Thermal Information: VQFN
    6. 7.6  Electrical Characteristics: ADS7950, ADS7951, ADS7952, ADS7953
    7. 7.7  Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957
    8. 7.8  Electrical Characteristics, ADS7958, ADS7959, ADS7960, ADS7961
    9. 7.9  Timing Requirements
    10. 7.10 Typical Characteristics (All ADS79xx Family Devices)
    11. 7.11 Typical Characteristics (12-Bit Devices Only)
    12. 7.12 Typical Characteristics (12-Bit Devices Only)
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Reference
      2. 8.3.2 Power Saving
    4. 8.4 Device Functional Modes
      1. 8.4.1 Channel Sequencing Modes
      2. 8.4.2 Device Programming and Mode Control
        1. 8.4.2.1 Mode Control Register
        2. 8.4.2.2 Program Registers
      3. 8.4.3 Device Power-Up Sequence
      4. 8.4.4 Operating in Manual Mode
      5. 8.4.5 Operating in Auto-1 Mode
      6. 8.4.6 Operating in Auto-2 Mode
      7. 8.4.7 Continued Operation in a Selected Mode
    5. 8.5 Programming
      1. 8.5.1 Digital Output
      2. 8.5.2 GPIO Registers
      3. 8.5.3 Alarm Thresholds for GPIO Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Analog Input
    2. 9.2 Typical Applications
      1. 9.2.1 Unbuffered Multiplexer Output (MXO)
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 OPA192 Buffered Multiplexer Output (MXO)
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Examples
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 関連リンク
    3. 12.3 ドキュメントの更新通知を受け取る方法
    4. 12.4 コミュニティ・リソース
    5. 12.5 商標
    6. 12.6 静電気放電に関する注意事項
    7. 12.7 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • RHB|32
  • DBT|38
サーマルパッド・メカニカル・データ
発注情報

7.7 Electrical Characteristics, ADS7954, ADS7955, ADS7956, ADS7957

+VA = 2.7 V to 5.25 V, +VBD = 1.7 V to +VA, VREF = 2.5 V ± 0.1 V, TA = –40°C to 125°C, fsample = 1 MHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
Full-scale input span(1) Range 1 0 VREF V
Range 2 while 2xVREF ≤ +VA 0 2*VREF
Absolute input range Range 1 –0.20 VREF +0.20 V
Range 2 while 2xVREF ≤ +VA –0.20 2*VREF +0.20
Input capacitance 15 pF
Input leakage current TA = 125°C 61 nA
SYSTEM PERFORMANCE
Resolution 10 Bits
No missing codes 10 Bits
Integral linearity –0.5 ±0.2 0.5 LSB(2)
Differential linearity –0.5 ±0.2 0.5 LSB
Offset error(3) –1.5 ±0.5 1.5 LSB
Gain error Range 1 –1 ±0.1 1 LSB
Range 2 ±0.1
SAMPLING DYNAMICS
Conversion time 20 MHz SCLK 800 ns
Acquisition time 325 ns
Maximum throughput rate 20 MHz SCLK 1 MHz
Aperture delay 5 ns
Step response 150 ns
Overvoltage recovery 150 ns
DYNAMIC CHARACTERISTICS
Total harmonic distortion(4) 100 kHz –80 dB
Signal-to-noise ratio 100 kHz 60 dB
Signal-to-noise + distortion 100 kHz 60
Spurious free dynamic range 100 kHz 82 dB
Full power bandwidth At –3 dB 47 MHz
Channel-to-channel crosstalk Any off-channel with 100 kHz, Full-scale input to channel being sampled with DC input. –95 dB
From previously sampled to channel with 100 kHz, Full-scale input to channel being sampled with DC input. –85
EXTERNAL REFERENCE INPUT
VREF reference voltage at REFP 2 2.5 3 V
Reference input resistance fsample = 1 MHz 100 kΩ
ALARM SETTING
High threshold range 000 4092 LSB
Low threshold range 000 4092 LSB
DIGITAL INPUT/OUTPUT
Logic family CMOS
Logic level VIH 0.7*(+VBD) V
VIL +VBD = 5 V 0.8
VIL +VBD = 3 V 0.4
VOH At Isource = 200 μA +VBD-0.2
VOL At Isink = 200 μA 0.4
Data format MSB first MSB First
POWER SUPPLY REQUIREMENTS
+VA supply voltage 2.7 3.3 5.25 V
+VBD supply voltage 1.7 3.3 5.25 V
Supply current (normal mode) At +VA = 2.7 to 3.6 V and 1MHz throughput 1.8 mA
At +VA = 2.7 to 3.6 V static state 1.05 1
At +VA = 4.7 to 5.25 V and 1 MHz throughput 2.3 3
At +VA = 4.7 to 5.25 V static state 1.1 1.5
Power-down state supply current 1 μA
+VBD supply current +VA = 5.25V, fs = 1MHz 1 mA
Power-up time 1 μs
Invalid conversions after power up or reset 1 Conversion
(1) Ideal input span; does not include gain or offset error.
(2) LSB means least significant bit.
(3) Measured relative to an ideal full-scale input.
(4) Calculated on the first nine harmonics of the input frequency.