ADS85x8 12、14、16ビット、8チャネル同時サンプリングADC

9.3.1.1 Analog Inputs

The inputs and the converters are of single-ended bipolar type. The absolute voltage range can be selected using the RANGE pin (in hardware mode) or RANGE_x bits (in software mode) in the Configuration (CONFIG) register to either ±4 VREF or ±2 VREF. With the internal reference set to 2.5 V (VREF bit C13 = 0 in the CONFIG register), the input voltage range can be ±10 V or ±5 V. With the internal reference source set to 3 V (CONFIG bit C13 = 1), an input voltage range of ±12 V or ±6 V can be configured. The logic state of the RANGE pin is latched with the falling edge of BUSY (if CONFIG bit C26 = 0).

The input current on the analog inputs depends on the actual sample rate, input voltage, and signal source impedance. Essentially, the current into the analog inputs charges the internal capacitor array only during the sampling period (t_ACQ). The source of the analog input voltage must be able to charge the input capacitance of 10 pF in ±4-VREF mode or of 20 pF in ±2-VREF mode to a 12-, 14-, or 16-bit accuracy level within the acquisition time; see Figure 35. During the conversion period, there is no further input current flow and the input impedance is greater than 1 MΩ. To ensure a defined start condition, the sampling capacitors of the ADS85x8 are pre-charged to a fixed internal voltage before switching into sampling mode.

To maintain the linearity of the converter, the inputs must always remain within the specified range defined in the Electrical Characteristics table. The minimum –3-dB bandwidth of the driving operational amplifier can be calculated using Equation 1:

Equation 1.

where

• n = 12, 14, or 16; n is the resolution of the ADS85x8

With a minimum acquisition time of t_ACQ = 280 ns, the required minimum bandwidth of the driving amplifier is 5.2 MHz for the ADS8528, 6.0 MHz for the ADS8548, or 6.7 MHz for the ADS8568. The required bandwidth can be lower if the application allows a longer acquisition time. A gain error occurs if a given application does not fulfill the bandwidth requirement shown in Equation 1.

A driving operational amplifier may not be required if the impedance of the signal source (R_SOURCE) fulfills the requirement of Equation 2:

Equation 2.

where

• n = 12, 14, or 16; n is the resolution of the ADC
• C_S = 10 pF is the sample capacitor value in V_IN = ±4-VREF mode
• R_SER = 200 Ω is the input resistor value
• and R_SW = 130 Ω is the switch resistance value

With a minimum acquisition time of t_ACQ = 280 ns, the maximum source impedance must be less than 2.7 kΩ for the ADS8528, 2.3 kΩ for the ADS8548, and 2.0 kΩ for the ADS8568 in ±4V-REF mode, or less than 1.2 kΩ for the ADS8528, 1.0 kΩ for the ADS8548, and 0.8 kΩ for the ADS8568 in ±2-VREF mode. The source impedance can be higher if the application allows a longer acquisition time.

9.3.1.2 Analog-to-Digital Converter (ADC)

The device includes eight ADCs that operate with either an internal or an external conversion clock.

9.3.1.3 Conversion Clock

The device uses either an internally-generated (CCLK) or an external (XCLK) conversion clock signal (in software mode only). In default mode, the device generates an internal clock. In this case, a complete conversion including the pre-charging of the sample capacitors takes 19 to 20 clock cycles, depending on the setup time of the incoming CONVST_x signal with relation to the CCLK rising edge.

When the CLKSEL bit is set high (CONFIG bit C29), an external conversion clock can be applied on pin 34. A complete conversion process requires 19 clock cycles in this case if the t_SCVX timing requirement is fulfilled. The external clock can remain low between conversions.

If the application requires lowest power dissipation at low data rates, using the auto-sleep mode activated with pin 36 (ASLEEP) is recommended. In this case, a conversion cycle takes up to 26 clock cycles (see the Reset and Power-Down Modes section for more details).

9.3.1.4 CONVST_x

The analog inputs of each channel pair (CH_x0, CH_x1) are held with the rising edge of the corresponding CONVST_x signal. The conversion automatically starts with the next rising edge of the conversion clock. CONVST_A is a master conversion start that resets the internal state machine and causes the data output to start with the result of channel A0. In cases where channel pairs of the device are used at different data rates, CONVST_A must always be the one used at the highest frequency.

A conversion start must not be issued during an ongoing conversion on the corresponding channel pair. However, conversions are allowed to be initiated on other input pairs; see the Sequential Operation section for more details.

If a parallel interface is used, the content of the output port depends on which CONVST_x signals are issued. Figure 36 shows examples of different scenarios with all channel pairs active.

Figure 36. Data Output versus CONVST_x (All Channels Active)

9.3.1.5 Data Readout and BUSY/INT Signal

The BUSY signal indicates if a conversion is in progress. The BUSY signal goes high with a rising edge of any CONVST_x signal and returns low again when the last channel pair completes the conversion cycle.

When operating the device with an external clock (CONFIG bit 29, CLKSEL = 1), data readout can be initiated immediately after the falling edge of the BUSY signal or after 19 complete conversion clock cycles (XCLK), respectively.

When using the device with an internal conversion clock (CONFIG bit 29, CLKSEL = 0), data can be retrieved after t_CONV(max) independently from the BUSY signal. In case the data readout is referred to the falling edge of the BUSY signal, the readout sequence cannot start before t_BUFS/BUCS after the falling edge, corresponding to 1 CCLK cycle (for example, 86 ns for the ADS8568).

In contrast, the INT signal goes high when a new conversion result is loaded in the output register (which occurs when the conversion completes) and remains high until the next read access, as shown in Figure 37.

The polarity of the BUSY/INT signal can be changed using CONFIG bit C26. The mode of pin 35 can be controlled using CONFIG bit C27.

Figure 37. BUSY versus INT Behavior of Pin 35

9.3.1.6 Sequential Operation

The four channel pairs of the ADS8528, ADS8548, and ADS8568 can run in sequential mode, with the corresponding CONVST_x signals interleaved. In this case, the BUSY output transitions low for a single conversion clock cycle (t_CCLK) whenever a channel pair completes a conversion. BUSY finally remains low when the conversion of the last channel pair completes. Figure 38 shows the behavior of the BUSY output in this mode.

NOTE:

EOC = end of conversion (internal signal).

Figure 38. Sequential Operation Timing Diagram

For best performance, operation with an external clock is recommended (CONFIG bit 29, CLKSEL = 1). Initiate each conversion start during the high phase of the external clock; see Figure 40.

The time between two CONVST_x pulses must be at least one conversion clock cycle. In case the skew of the CONVST_x signals is less than one conversion clock cycle, the data readout cannot be started before t_CCLK after the falling edge of the BUSY signal.

9.3.1.7 Reference

The ADS85x8 provides an internal, low-drift, 2.5-V reference source. To increase the input voltage range, the reference voltage can be switched to 3-V mode using the VREF bit (CONFIG bit C13). The reference feeds a 10-bit string-DAC controlled by the REFDAC[9:0] bits in the Configuration (CONFIG) register. The buffered DAC output is connected to the REFIO pin. In this way, the voltage at this pin is programmable in 2.44-mV steps (2.92 mV in 3-V mode) and adjustable to the applications needs without additional external components. The actual output voltage can be calculated using Equation 3:

Equation 3.

where

• Range = the chosen maximum reference voltage output range (2.5 V or 3 V)
• Code = the decimal value of the DAC register content

Table 1 lists some examples of internal reference DAC settings with a reference range set to 2.5 V. However, to ensure proper performance, the DAC output voltage must not be programmed below 0.5 V.

Decouple the buffered output of the DAC with a 100-nF capacitor (minimum); for best performance, a 470-nF capacitor is recommended. If the internal reference is placed into power-down (default), an external reference voltage can drive the REFIO pin.

The voltage at the REFIO pin is buffered with four internal amplifiers, one for each ADC pair. The output of each buffer must be decoupled with a 10-µF capacitor between the pin pairs of 3 and 6, 43 and 46, 50 and 53, and 60 and 63. The 10-µF capacitors are available as ceramic 0805-SMD components and in X5R quality.

The internal reference buffers can be powered down to decrease the power dissipation of the device. In this case, external reference drivers can be connected to the REFAP, REFBP, REFCP, and REFDP pins. With 10-µF decoupling capacitors, the minimum required bandwidth can be calculated using Equation 4:

Equation 4.

With the minimum t_CONV of 1.33 µs, the external reference buffers require a minimum bandwidth of 83 kHz.

9.3.2.1 Device Configuration

Depending on the desired mode of operation, the ADS85x8 can be configured using the external pins or the Configuration register (CONFIG), as shown in Table 2.

9.3.2.2 Parallel Interface

To use the device with the parallel interface, hold the PAR/SER pin low. The maximum achievable data throughput rate is 650 kSPS for the ADS8528, 600 kSPS for the ADS8548, and 510 kSPS for the ADS8568 in this case.

Access to the ADS85x8 is controlled as illustrated in Figure 2 and Figure 3.

9.3.2.3 Serial Interface

The serial interface mode is selected by setting the PAR/SER pin high. In this case, each data transfer starts with the falling edge of the frame synchronization input (FS). The conversion results are presented on the serial data output pins SDO_A (always active), SDO_B, SDO_C, and SDO_D, depending on the selections made using the SEL_xx pins. Starting with the most significant bit (MSB), the output data are changed with the SCLK falling edge. The ADS8528 and ADS8548 output data maintain the LSB-aligned, 16-bit format with leading bits containing the extended sign (see Table 3). Serial data input SDI are latched with the SCLK falling edge.

The serial interface can be used with one, two, or four output ports. Port SDO_B can be enabled using pin 27 (SEL_B) and ports SDO_C and SDO_D are enabled using pin 28 (SEL_CD). If all four serial data output ports are selected, data can be read with either two 16-bit data transfers or with a single 32-bit data transfer. The data of channels CH_x0 are available first, followed by data from channels CH_x1. The maximum achievable data throughput rate is 480 kSPS for the ADS8528, 450 kSPS for the ADS8548, and 400 kSPS for the ADS8568 in this case.

If the application allows a data transfer using two ports only, the SDO_A and SDO_B outputs are used. The device outputs data from channel CH_A0 followed by CH_A1, CH_C0, and CH_C1 on SDO_A; data from channel CH_B0 followed by CH_B1, CH_D0, and CH_D1 occur on SDO_B. In this case, a data transfer of four 16-bit words, two 32-bit words, or one continuous 64-bit word is supported. The maximum achievable data throughput rate is 360 kSPS for the ADS8528, 345 kSPS for the ADS8548, and 315 kSPS for the ADS8568 in this case.

The output SDO_A is always active and exclusively used if only one serial data port is used in the application. Data are available in the following order: CH_A0, CH_A1, CH_B0, CH_B1, CH_C0, CH_C1, CH_D0, and CH_D1. Data can be read using eight 16-bit transfers, four 32-bit transfers, two 64-bit transfers, or a single 128-bit transfer. The maximum achievable data throughput rate is 235 kSPS for the ADS8528, 230 kSPS for the ADS8548 and 215 kSPS for the ADS8568 in this case. Figure 1 and Figure 39 illustrate all possible scenarios in more detail.

Figure 39. Data Output with One or Two Active SDOs (All Input Channels Active and Converted)

9.3.2.4 Output Data Format

The data output format of the ADS85x8 is binary twos complement, as shown in Table 3. For the ADS8528 and ADS8548 (that deliver 12-bit or 14-bit conversion results, respectively), the leading bits of either the 16-bit frame (serial interface) or the output pins (DB[15:12] for the ADS8528 or DB[15:14] for the ADS8548 in parallel mode) deliver a sign extension.

Table 4. Maximum Analog Current (IAVDD) Demand of the ADS85x8

9.5.1.1 CONFIG: Configuration Register (default = 000003FFh)