JAJSD75C August   2011  – February 2016 ADS8528 , ADS8548 , ADS8568

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics: General
    6. 7.6  Electrical Characteristics: ADS8528
    7. 7.7  Electrical Characteristics: ADS8548
    8. 7.8  Electrical Characteristics: ADS8568
    9. 7.9  Serial Interface Timing Requirements
    10. 7.10 Parallel Interface Timing Requirements (Read Access)
    11. 7.11 Parallel Interface Timing Requirements (Write Access)
    12. 7.12 Typical Characteristics
  8. 8 Parameter Measurement information
    1. 8.1 Equivalent Circuits
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Analog
        1. 9.3.1.1 Analog Inputs
        2. 9.3.1.2 Analog-to-Digital Converter (ADC)
        3. 9.3.1.3 Conversion Clock
        4. 9.3.1.4 CONVST_x
        5. 9.3.1.5 Data Readout and BUSY/INT Signal
        6. 9.3.1.6 Sequential Operation
        7. 9.3.1.7 Reference
      2. 9.3.2 Digital
        1. 9.3.2.1 Device Configuration
        2. 9.3.2.2 Parallel Interface
        3. 9.3.2.3 Serial Interface
        4. 9.3.2.4 Output Data Format
    4. 9.4 Device Functional Modes
      1. 9.4.1 Hardware Mode
      2. 9.4.2 Software Mode
      3. 9.4.3 Daisy-Chain Mode
      4. 9.4.4 Reset and Power-Down Modes
    5. 9.5 Register Maps
      1. 9.5.1 Configuration (CONFIG) Register
        1. 9.5.1.1 CONFIG: Configuration Register (default = 000003FFh)
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curve
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13デバイスおよびドキュメントのサポート
    1. 13.1 ドキュメントのサポート
      1. 13.1.1 関連資料
    2. 13.2 関連リンク
    3. 13.3 コミュニティ・リソース
    4. 13.4 商標
    5. 13.5 静電気放電に関する注意事項
    6. 13.6 Glossary
  14. 14メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6 Pin Configuration and Functions

RGC Package
64-Pin VQFN
Top View
ADS8528 ADS8548 ADS8568 po_rgc_bas543.gif
PM Package
64-Pin LQFP
Top View
ADS8528 ADS8548 ADS8568 po_pm_bas543.gif

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO. PARALLEL INTERFACE (PAR/SER = 0) SERIAL INTERFACE (PAR/SER = 1)
AGND 5, 15, 44, 51, 58, 62 P Analog ground; connect to the analog ground plane.
ASLEEP 36 DI Auto-sleep enable input.
When low, the device operates in normal mode.
When high, the device functions in auto-sleep mode where the hold mode and the actual conversion is activated six conversion clock (tCCLK) cycles after issuing a conversion start using a CONVST_x. This mode is recommended to save power if the device runs at a lower data rate; see the Reset and Power-Down Modes section for more details.
AVDD 4, 14, 45, 52, 57, 61 P Analog power supply.
Decouple according to the Power Supply Recommendations section.
BUSY/INT 35 DO When CONFIG bit C27 = 0 (BUSY/INT), this pin is a converter busy status output.
This pin transitions high when a conversion is started and transitions low for a single conversion clock cycle (tCCLK) whenever a channel pair conversion is completed and stays low when the conversion of the last channel pair completes.
When bit C27 = 1 (BUSY/INT in CONFIG), this pin is an interrupt output. This pin transitions high after a conversion completes and remains high until the next read access. This mode can only be used if all eight channels are sampled simultaneously (all CONVST_x tied together). The polarity of the BUSY/INT output can be changed using the C26 bit (BUSY L/H) in the Configuration register.
CH_A0 42 AI Analog input of channel A0; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by Configuration register (CONFIG) bit C24 (RANGE_A) in software mode. In cases where channel pairs of the device are used at different data rates, channel pair A must always run at the highest data rate.
CH_A1 47 AI Analog input of channel A1; channel A is the master channel pair that is always active.
The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C24 (RANGE_A) in software mode. In cases where channel pairs of the device are used at different data rates, channel pair A must always run at the highest data rate.
CH_B0 49 AI Analog input of channel B0. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in software mode.
CH_B1 54 AI Analog input of channel B1. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C23 (RANGE_B) in software mode.
CH_C0 64 AI Analog input of channel C0. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in software mode.
CH_C1 59 AI Analog input of channel C1. The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C21 (RANGE_C) in software mode.
CH_D0 7 AI Analog input of channel D0.The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in software mode.
CH_D1 2 AI Analog input of channel D1.The input voltage range is controlled by the RANGE pin in hardware mode or by CONFIG bit C19 (RANGE_D) in software mode. This pin can be powered down using CONFIG bit C18 (PD_D) in software mode.
CONVST_A 37 DI Conversion start of channel pair A.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_A[1:0].
This signal resets the internal channel state machine that causes the data output to start with conversion results of channel A0 with the next read access.
CONVST_B 38 DI Conversion start of channel pair B.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_B[1:0].
CONVST_C 39 DI Conversion start of channel pair C.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_C[1:0].
CONVST_D 40 DI Conversion start of channel pair D.
The rising edge of this signal initiates simultaneous conversion of analog signals at inputs CH_D[1:0].
CS/FS 13 DI, DI Chip-select input.
When low, the parallel interface is enabled. When high, the interface is disabled.		 Frame synchronization.
The FS falling edge controls the frame transfer.
DB0/DCIN_D 33 DIO, DI Data bit 0 (LSB) input/output When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data input for SDO_D of the previous device in the chain.
When DCEN = 0, connect to DGND.
DB1/DCIN_C 32 DIO, DI Data bit 1 input/output When DCEN = 1 and SEL_CD = 1, this pin is the daisy-chain data input for SDO_C of the previous device in the chain.
When DCEN = 0, connect to DGND.
DB2/DCIN_B 31 DIO, DI Data bit 2 input/output When DCEN = 1 and SEL_B = 1, this pin is the daisy-chain data input for SDO_B of the previous device in the chain.
When DCEN = 0, connect to DGND.
DB3/DCIN_A 30 DIO, DI Data bit 3 input/output When DCEN = 1, this pin is the daisy-chain data input for SDO_A of the previous device in the chain. When DCEN = 0, connect to DGND.
DB4 29 DIO Data bit 4 input/output Connect to DGND
DB5/SEL_CD 28 DIO, DI Data bit 5 input/output Select SDO_C and SDO_D input.
When high, data from channel pair C are available on SDO_C and data from channel pair D are available on SDO_D. When low and SEL_B = 1, data from channel pairs A and C are available on SDO_A and data from channel pairs B and D are available on SDO_B. When low and SEL_B = 0, data from all eight channels are available on SDO_A.
DB6/SEL_B 27 DIO, DI Data bit 6 input/output Select SDO_B input.
When low, SDO_B is disabled and data from all eight channels are only available through SDO_A.
When high and SEL_CD = 0, data from channel pairs B and D are available on SDO_B. When SEL_CD = 1, data from channel pair B are available on SDO_B.
DB7 26 DIO Data bit 7 input/output Must be connected to DGND
DB8/DCEN 23 DIO, DI Data bit 8 input/output Daisy-chain enable input.
When high, DB[3:0] serve as daisy-chain inputs DCIN_[A:D].
If daisy-chain mode is not used, connect to DGND.
DB9/SDI 22 DIO, DI Data bit 9 input/output Hardware mode (HW/SW = 0): connect to DGND.
Software mode (HW/SW = 1): serial data input.
DB10/SCLK 21 DIO, DI Data bit 10 input/output Serial interface clock input.
DB11/
REFBUFEN		 20 DIO, DI Data bit 11 input/output.
Output is MSB for the ADS8528.		 Hardware mode (HW/SW = 0): reference buffer enable input.
When low, all internal reference buffers are enabled (mandatory if internal reference is used).
When high, all reference buffers are disabled.
Software mode (HW/SW = 1): connect to DGND or DVDD.
The internal reference buffers are controlled by CONFIG bit C14 (REFBUFEN).
DB12/SDO_A 19 DIO, DO Data bit 12 input/output.
Output is sign extension for the ADS8528.		 Data output for channel pair A.
When SEL_CD = 0, data from channel pair C are also available on this output.
When SEL_CD = 0 and SEL_B = 0, SDO_A functions as single data output for all eight channels.
DB13/SDO_B 18 DIO, DO Data bit 13 input/output.
Output is sign extension for the ADS8528 and MSB for the ADS8548.		 When SEL_B = 1, this pin is the data output for channel pair B. When SEL_B = 0, tie this pin to DGND. When SEL_CD = 0, data from channel pair D are also available on this output.
DB14/SDO_C 17 DIO, DO Data bit 14 input/output.
Output is sign extension for the ADS8528 and ADS8548.		 When SEL_CD = 1, this pin is the data output for channel pair C.
When SEL_CD = 0, tie this pin to DGND.
DB15/SDO_D 16 DIO, DO Data bit 15 (MSB) input/output.
Output is sign extension for the ADS8528 and ADS8548.		 When SEL_CD = 1, this pin is the data output for channel pair D.
When SEL_CD = 0, tie this pin to DGND.
DGND 24 P Buffer I/O ground, connect to digital ground plane
DVDD 25 P Buffer I/O supply, connect to digital supply.
Decouple according to the Power Supply Recommendations section.
HVDD 48 P Positive supply voltage for the analog inputs.
Decouple according to the Power Supply Recommendations section.
HVSS 1 P Negative supply voltage for the analog inputs.
Decouple according to the Power Supply Recommendations section.
HW/SW 41 DI Mode selection input.
When low, hardware mode is selected and the device functions according to the settings of the external pins. When high, software mode is selected and the device is configured by writing to the Configuration register (CONFIG).
PAR/SER 8 DI Interface mode selection input.
When low, the parallel interface is selected. When high, the serial interface is enabled.
RANGE/XCLK 34 DI/DI/DO Hardware mode (HW/SW = 0): analog input voltage range select input.
When low, the analog input voltage range is ±4 VREF. When high, the analog input voltage range is ±2 VREF.
Software mode (HW/SW = 1): this pin is an external conversion clock input if CONFIG bit C29 = 1 (CLKSEL); or an internal conversion clock output if CONFIG bit C28 = 1 (CLKOUT_EN).
If this pin is not used, connect to DGND.
RD 12 DI/DI Read data input.
When low, the parallel data output is enabled (if CS = 0). When high, the data output is disabled.		 Must be connected to DGND.
REFAN 46 AI Decoupling capacitor input for reference of channel pair A.
Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.
REFAP 43 AI Decoupling capacitor input for reference of channel pair A.
Connect to the decoupling capacitor according to the Power Supply Recommendations section.
REFBN 53 AI Decoupling capacitor input for reference of channel pair B.
Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.
REFBP 50 AI Decoupling capacitor input for reference of channel pair B.
Connect to the decoupling capacitor according to the Power Supply Recommendations section.
REFCN 60 AI Decoupling capacitor input for reference of channel pair C.
Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.
REFCP 63 AI Decoupling capacitor input for reference of channel pair C.
Connect to the decoupling capacitor according to the Power Supply Recommendations section.
REFDN 3 AI Decoupling capacitor input for reference of channel pair D.
Connect to the decoupling capacitor and AGND according to the Power Supply Recommendations section.
REFDP 6 AI Decoupling capacitor input for the channel pair D reference.
Connect to the decoupling capacitor according to the Power Supply Recommendations section.
REFEN/WR 11 DI/DI Hardware mode (HW/SW = 0): internal reference enable input.
When high, the internal reference is enabled (the reference buffers are also enabled).
When low, the internal reference is disabled and an external reference is applied at REFIO.		 Hardware mode (HW/SW = 0): internal reference enable input.
When high, the internal reference is enabled (the reference buffers are also enabled).
When low, the internal reference is disabled and an external reference is applied at REFIO.
Software mode (HW/SW = 1): write input.
The parallel data input is enabled when CS and WR are low. The internal reference is enabled by CONFIG bit C15 (REFEN).		 Software mode (HW/SW = 1): connect to DGND or DVDD. The internal reference is enabled by CONFIG bit C15 (REFEN).
REFIO 56 AIO Reference voltage input/output.
The internal reference is enabled by the REFEN/WR pin in hardware mode or by CONFIG bit C15 (REFEN) in software mode. The output value is controlled by the internal digital-to-analog converter (DAC), CONFIG bits
C[9:0]. Connect to a decoupling capacitor according to the Power Supply Recommendations section.
REFN 55 AI Negative reference input/output pin.
Connect to a decoupling capacitor and AGND according to the Power Supply Recommendations section.
RESET 10 DI Reset input, active high.
This pin aborts any ongoing conversions and resets the internal Configuration register (CONFIG) to 000003FFh.
A valid reset pulse must be at least 50 ns long.
STBY 9 DI Hardware mode (HW/SW = 0): standby mode input.
When low, the entire device is powered down (including the internal conversion clock source and reference).
When high, the device operates in normal mode.
Software mode (HW/SW = 1): connect to DGND or DVDD.
The standby mode can be activated using CONFIG bit C25 (STBY).
(1) AI = analog input; AIO = analog input/output; DI = digital input; DIO = digital input/output; DO = digital output; and P = power supply.