ADS867x 14-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar Input Ranges
- SBAS627 July 2015 ADS8674 , ADS8678
  
  PRODUCTION DATA.

Full reading width

DATA SHEET

ADS867x 14-Bit, 500-kSPS, 4- and 8-Channel, Single-Supply, SAR ADCs with Bipolar Input Ranges

1 Features

14-Bit ADCs with Integrated Analog Front-End
4-, 8-Channel MUX with Auto and Manual Scan
Channel-Independent Programmable Inputs:
- ±10.24 V, ±5.12 V, ±2.56 V, ±1.28 V, ±0.64 V
- 10.24 V, 5.12 V, 2.56 V, 1.28 V
5-V Analog Supply: 1.65-V to 5-V I/O Supply
Constant Resistive Input Impedance: 1 MΩ
Input Overvoltage Protection: Up to ±20 V
On-Chip, 4.096-V Reference with Low Drift
Excellent Performance:
- 500-kSPS Aggregate Throughput
- DNL: ±0.2 LSB; INL: ±0.25 LSB
- Low Drift for Gain Error and Offset
- SNR: 85 dB; THD: –100 dB
- Low Power: 65 mW
AUX Input → Direct Connection to ADC Inputs
ALARM → High and Low Thresholds per Channel
SPI™-Compatible Interface with Daisy-Chain
Industrial Temperature Range: –40°C to 125°C
TSSOP-38 Package (9.7 mm × 4.4 mm)

Block Diagram

ADS8674 ADS8678 frontpage_ads8678_sbas627.gif

2 Applications

Power Automation
Protection Relays
PLC Analog Input Modules

3 Description

The ADS8674 and ADS8678 are 4- and 8-channel, integrated data acquisition systems based on a 14-bit successive approximation (SAR) analog-to-digital converter (ADC), operating at a throughput of
500 kSPS. The devices feature integrated analog front-end circuitry for each input channel with overvoltage protection up to ±20 V, a 4- or 8-channel multiplexer with automatic and manual scanning modes, and an on-chip, 4.096-V reference with low temperature drift. Operating on a single 5-V analog supply, each input channel on the devices can support true bipolar input ranges of ±10.24 V,
±5.12 V, ±2.56 V, ±1.28V and ±0.64V, as well as unipolar input ranges of 0 V to 10.24 V, 0 V to 5.12 V, 0 V to 2.56 V and 0 V to 1.28 V. The gain of the analog front-end for all input ranges is accurately trimmed to ensure a high dc precision. The input range selection is software-programmable and independent for each channel. The devices offer a
1-MΩ constant resistive input impedance irrespective of the selected input range.

The ADS8674 and ADS8678 offer a simple SPI-compatible serial interface to the digital host and also support daisy-chaining of multiple devices. The digital supply operates from 1.65 V to 5.25 V, enabling direct interface to a wide range of host controllers.

Device Information⁽¹⁾

PART NUMBER	PACKAGE	BODY SIZE (NOM)
ADS867x	TSSOP (38)	9.70 mm × 4.40 mm

For all available packages, see the orderable addendum at the end of the datasheet.

Gain Error versus Temperature

4 Revision History

DATE	REVISION	NOTES
July 2014	*	Initial release.

5 Device Comparison Table

PRODUCT	RESOLUTION (Bits)	CHANNELS	SAMPLE RATE (kSPS)
ADS8674	14	4, single-ended	500
ADS8678	14	8, single-ended	500

6 Pin Configuration and Functions

DBT Package

38-Pin TSSOP

Top View (Not to Scale)

ADS8674 ADS8678 po_ads8674_ads8678_sbas627.gif

Pin Functions

PIN			I/O	DESCRIPTION
NO.	NAME
NO.	ADS8674	ADS8678
1	SDI		Digital input	Data input for serial communication.
2	RST/PD		Digital input	Active low logic input. Dual functionality to reset or power-down the device.
3	DAISY		Digital input	Chain the data input during serial communication in daisy-chain mode.
4	REFSEL		Digital input	Active low logic input to enable the internal reference. When low, the internal reference is enabled; REFIO becomes an output that includes the V_REF voltage. When high, the internal reference is disabled; REFIO becomes an input to apply the external V_REF voltage.
5	REFIO		Analog input, output	Internal reference output and external reference input pin. Decouple with REFGND on pin 6.
6	REFGND		Power supply	Reference GND pin; short to the analog GND plane. Decouple with REFIO on pin 5 and REFCAP on pin 7.
7	REFCAP		Analog output	ADC reference decoupling capacitor pin. Decouple with REFGND on pin 6.
8	AGND		Power supply	Analog ground pin. Decouple with AVDD on pin 9.
9	AVDD		Power supply	Analog supply pin. Decouple with AGND on pin 8.
10	AUX_IN		Analog input	Auxiliary input channel: positive input. Decouple with AUX_GND on pin 11.
11	AUX_GND		Analog input	Auxiliary input channel: negative input. Decouple with AUX_IN on pin 10.
12	NC	AIN_6P	Analog input	Analog input channel 6, positive input. Decouple with AIN_6GND on pin 13. No connection for the ADS8674; this pin can be left floating or connected to AGND.
13	NC	AIN_6GND	Analog input	Analog input channel 6, negative input. Decouple with AIN_6P on pin 12. No connection for the ADS8674; this pin can be left floating or connected to AGND.
14	NC	AIN_7P	Analog input	Analog input channel 7, positive input. Decouple with AIN_7GND on pin 15. No connection for the ADS8674; this pin can be left floating or connected to AGND.
15	NC	AIN_7GND	Analog input	Analog input channel 7, negative input. Decouple with AIN_7P on pin 14. No connection for the ADS8674; this pin can be left floating or connected to AGND.
16	AIN_0P		Analog input	Analog input channel 0, positive input. Decouple with AIN_0GND on pin 17.
17	AIN_0GND		Analog input	Analog input channel 0, negative input. Decouple with AIN_0P on pin 16.
18	AIN_1P		Analog input	Analog input channel 1, positive input. Decouple with AIN_1GND on pin 19.
19	AIN_1GND		Analog input	Analog input channel 1, negative input. Decouple with AIN_1P on pin 18.
20	AIN2_GND		Analog input	Analog input channel 2, negative input. Decouple with AIN_2P on pin 21.
21	AIN_2P		Analog input	Analog input channel 2, positive input. Decouple with AIN_2GND on pin 20.
22	AIN_3GND		Analog input	Analog input channel 3, negative input. Decouple with AIN_3P on pin 23.
23	AIN_3P		Analog input	Analog input channel 3, positive input. Decouple with AIN_3GND on pin 22.
24	NC	AIN_4GND	Analog input	Analog input channel 4, negative input. Decouple with AIN_4P on pin 25. No connection for the ADS8674; this pin can be left floating or connected to AGND.
25	NC	AIN_4P	Analog input	Analog input channel 4, positive input. Decouple with AIN_4GND on pin 24. No connection for the ADS8674; this pin can be left floating or connected to AGND.
26	NC	AIN_5GND	Analog input	Analog input channel 5, negative input. Decouple with AIN_5P on pin 27. No connection for the ADS8674; this pin can be left floating or connected to AGND.
27	NC	AIN_5P	Analog input	Analog input channel 5, positive input. Decouple with AIN_5GND on pin 26. No connection for the ADS8674; this pin can be left floating or connected to AGND.
28	AGND		Power supply	Analog ground pin
29	AGND		Power supply	Analog ground pin
30	AVDD		Power supply	Analog supply pin. Decouple with AGND on pin 31.
31	AGND		Power supply	Analog ground pin. Decouple with AVDD on pin 30.
32	AGND		Power supply	Analog ground pin
33	DGND		Power supply	Digital ground pin. Decouple with DVDD on pin 34.
34	DVDD		Power supply	Digital supply pin. Decouple with DGND on pin 33.
35	ALARM		Digital output	Active high alarm output
36	SDO		Digital output	Data output for serial communication
37	SCLK		Digital input	Clock input for serial communication
38	CS		Digital input	Active low logic input; chip-select signal

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

	MIN	MAX	UNIT
AIN_nP, AIN_nGND to GND⁽²⁾	–20	20	V
AIN_nP, AIN_nGND to GND⁽³⁾	–11	11	V
AUX_GND to GND	–0.3	0.3	V
AUX_IN to GND	–0.3	AVDD + 0.3	V
AVDD to GND or DVDD to GND	–0.3	7	V
REFCAP to REFGND or REFIO to REFGND	–0.3	5.7	V
GND to REFGND	–0.3	0.3	V
Digital input pins to GND	–0.3	DVDD + 0.3	V
Digital output pins to GND	–0.3	DVDD + 0.3	V
Operating temperature, T_A	–40	125	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) AVDD = 5 V or offers a low impedance of < 30 kΩ.

(3) AVDD = floating with an impedance > 30 kΩ.

7.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	Analog input pins (AIN_nP; AIN_nGND)	±4000	V
		Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	All other pins	±2000
		Charged device model (CDM), per JEDEC specification JESD22-C101⁽²⁾		±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
AVDD	Analog supply voltage	4.75	5	5.25	V
DVDD	Digital supply voltage	1.65	3.3	AVDD	V

7.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADS8674, ADS8678	UNIT
		DBT (TSSOP)
		38 PINS
R_θJA	Junction-to-ambient thermal resistance	68.8	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	19.9	°C/W
R_θJB	Junction-to-board thermal resistance	30.4	°C/W
ψ_JT	Junction-to-top characterization parameter	1.3	°C/W
ψ_JB	Junction-to-board characterization parameter	29.8	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	NA	°C/W

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

7.5 Electrical Characteristics

Minimum and maximum specifications are at T_A = –40°C to 125°C. Typical specifications are at T_A = 25°C.
AVDD = 5 V, DVDD = 3 V, V_REF = 4.096 V (internal), and f_SAMPLE = 500 kSPS, unless otherwise noted.

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT	TEST LEVEL⁽¹⁾
ANALOG INPUTS
	Full-scale input span⁽²⁾ (AIN_nP to AIN_nGND)		Input range = ±2.5 × V_REF	–2.5 × V_REF		2.5 × V_REF	V	A
			Input range = ±1.25 × V_REF	–1.25 × V_REF		1.25 × V_REF		A
			Input range = ±0.625 × V_REF	–0.625 × V_REF		0.625 × V_REF		A
			Input range = ±0.3125 × V_REF	–0.3125 × V_REF		0.3125 × V_REF		A
			Input range = ±0.15625 × V_REF	–0.15625 × V_REF		0.15625 × V_REF		A
			Input range = 2.5 × V_REF	0		2.5 × V_REF		A
			Input range = 1.25 × V_REF	0		1.25 × V_REF		A
			Input range = 0.625 × V_REF	0		0.625 × V_REF		A
			Input range = 0.3125 × V_REF	0		0.3125 × V_REF		A
AIN_nP	Operating input range, positive input		Input range = ±2.5 × V_REF	–2.5 × V_REF		2.5 × V_REF	V	A
			Input range = ±1.25 × V_REF	–1.25 × V_REF		1.25 × V_REF		A
			Input range = ±0.625 × V_REF	–0.625 × V_REF		0.625 × V_REF		A
			Input range = ±0.3125 × V_REF	–0.3125 × V_REF		0.3125 × V_REF		A
			Input range = ±0.15625 × V_REF	–0.15625 × V_REF		0.15625 × V_REF		A
			Input range = 2.5 × V_REF	0		2.5 × V_REF		A
			Input range = 1.25 × V_REF	0		1.25 × V_REF		A
			Input range = 0.625 × V_REF	0		0.625 × V_REF		A
			Input range = 0.3125 × V_REF	0		0.3125 × V_REF		A
AIN_nGND	Operating input range, negative input		All input ranges	–0.1	0	0.1	V	B
z_i	Input impedance		At T_A = 25°C, all input ranges	0.85	1	1.15	MΩ	B
	Input impedance drift		All input ranges		7	25	ppm/°C	B
I_Ikg(in)	Input leakage current		With voltage at AIN_nP pin = V_IN, input range = ±2.5 × V_REF		V_IN – 2.25 ———— R_IN		µA	A
			With voltage at AIN_nP pin = V_IN, input range = ±1.25 × V_REF		V_IN – 2.00 ———— R_IN			A
			With voltage at AIN_nP pin = V_IN, input ranges = ±0.625 × V_REF; ±0.3125 × V_REF; ±0.15625 × V_REF		V_IN – 1.60 ———— R_IN			A
			With voltage at AIN_nP pin = V_IN, input range = 2.5 × V_REF		V_IN – 2.50 ———— R_IN			A
			With voltage at AIN_nP pin = V_IN, input range = 1.25 × V_REF; 0.625 × V_REF; 0.3125 × V_REF		V_IN – 2.50 ———— R_IN			A
INPUT OVERVOLTAGE PROTECTION
V_OVP	Overvoltage protection voltage		AVDD = 5 V or offers low impedance < 30 kΩ, all input ranges	–20		20	V	B
V_OVP	Overvoltage protection voltage		AVDD = floating with impedance > 30 kΩ, all input ranges	–11		11	V	B
SYSTEM PERFORMANCE
	Resolution			14			Bits	A
NMC	No missing codes			14			Bits	A
DNL	Differential nonlinearity			–0.5	±0.2	0.5	LSB⁽³⁾	A
INL	Integral nonlinearity⁽⁶⁾			–0.75	±0.25	0.75	LSB	A
E_G	Gain error		At T_A = 25°C, all input ranges		±0.02	±0.05	%FSR⁽⁴⁾	A
	Gain error matching (channel-to-channel)		At T_A = 25°C, all input ranges		±0.02	±0.05	%FSR	A
	Gain error temperature drift		All input ranges		1	4	ppm/°C	B
E_O	Offset error		At T_A = 25°C, input range = ±2.5 × V_REF⁽¹⁰⁾		±0.5	±1	mV	A
E_O	Offset error		At T_A = 25°C, all other input ranges		±0.5	±2	mV	A
	Offset error matching (channel-to-channel)		At T_A = 25°C, input range = ±2.5 × V_REF⁽¹⁰⁾		±0.5	±1	mV	A
	Offset error matching (channel-to-channel)		At T_A = 25°C, all other input ranges		±0.5	±2	mV	A
	Offset error temperature drift		Input range = ±2.5 × V_REF		1	3	ppm/°C	B
			Input range = ±1.25 × V_REF		1	3		B
			Input range = ±0.625 × V_REF		1	3		B
			Input range = ±0.3125 × V_REF		2	6		B
			Input range = ±0.15625 × V_REF		4	12		B
			Input range = 0 to 2.5 × V_REF		1	3		B
			Input range = 0 to 1.25 × V_REF		1	3		B
			Input range = 0 to 0.625 × V_REF		2	6		B
			Input range = 0 to 0.3125 × V_REF		4	12		B
SAMPLING DYNAMICS
t_CONV	Conversion time					850	ns	A
t_ACQ	Acquisition time			1150			ns	A
f_S	Maximum throughput rate without latency					500	kSPS	A
DYNAMIC CHARACTERISTICS
SNR	Signal-to-noise ratio (V_IN – 0.5 dBFS at 1 kHz)		Input range = ±2.5 × V_REF	84.5	85		dB	A
			Input range = ±1.25 × V_REF	84.2	85			A
			Input range = ±0.625 × V_REF	83.5	84.5			A
			Input range = ±0.3125 × V_REF	80	82			A
			Input range = ±0.15625 × V_REF	75	77			A
			Input range = 2.5 × V_REF	84	85			A
			Input range = 1.25 × V_REF	83.5	84.5			A
			Input range = 0.625 × V_REF	80	82			A
			Input range = 0.3125 × V_REF	75	77			A
THD	Total harmonic distortion⁽⁵⁾ (V_IN – 0.5 dBFS at 1 kHz)		All input ranges		–100		dB	B
SINAD	Signal-to-noise ratio (V_IN – 0.5 dBFS at 1 kHz)		Input range = ±2.5 × V_REF	84.3	84.8		dB	A
			Input range = ±1.25 × V_REF	84	84.8			A
			Input range = ±0.625 × V_REF	83.3	84.3			A
			Input range = ±0.3125 × V_REF	80	82			A
			Input range = ±0.15625 × V_REF	75	77			A
			Input range = 2.5 × V_REF	83.8	84.8			A
			Input range = 1.25 × V_REF	83.3	84.3			A
			Input range = 0.625 × V_REF	80	82			A
			Input range = 0.3125 × V_REF	75	77			A
SFDR	Spurious-free dynamic range (V_IN – 0.5 dBFS at 1 kHz)		All input ranges		101		dB	B
	Crosstalk isolation⁽⁷⁾		Aggressor channel input overdriven to 2 × maximum input voltage		110		dB	B
	Crosstalk memory⁽⁸⁾		Aggressor channel input overdriven to 2 × maximum input voltage		90		dB	B
BW_{(–3 dB)}	Small-signal bandwidth, –3 dB		At T_A = 25°C, all input ranges		15		kHz	B
BW_{(–0.1 dB)}	Small-signal bandwidth, –0.1 dB		At T_A = 25°C, all input ranges		2.5		kHz	B
AUXILIARY CHANNEL
	Resolution			14			Bits	A
V_{(AUX_IN)}	AUX_IN voltage range		(AUX_IN – AUX_GND)	0		V_REF	V	A
	Operating input range		AUX_IN	0		V_REF	V	A
	Operating input range		AUX_GND		0		V	A
C_i	Input capacitance		During sampling		75		pF	C
C_i	Input capacitance		During conversion		5		pF	C
I_Ikg(in)	Input leakage current				100		nA	A
DNL	Differential nonlinearity			–0.75	±0.5	0.75	LSB	A
INL	Integral nonlinearity			–1	±0.5	1	LSB	A
E_G(AUX)	Gain error		At T_A = 25°C		±0.02	±0.2	%FSR	A
E_O(AUX)	Offset error		At T_A = 25°C	–5		5	mV	A
SNR	Signal-to-noise ratio		V_{(AUX_IN)} = –0.5 dBFS at 1 kHz	83.3	84.4		dB	A
THD	Total harmonic distortion⁽⁵⁾		V_{(AUX_IN)} = –0.5 dBFS at 1 kHz		–100		dB	B
SINAD	Signal-to-noise + distortion		V_{(AUX_IN)} = –0.5 dBFS at 1 kHz	83	84.3		dB	A
SFDR	Spurious-free dynamic range		V_{(AUX_IN)} = –0.5 dBFS at 1 kHz		100		dB	B
INTERNAL REFERENCE OUTPUT
V_{(REFIO_INT)}⁽⁹⁾	Voltage on REFIO pin (configured as output)		At T_A = 25°C	4.094	4.096	4.098	V	A
	Internal reference temperature drift				8	20	ppm/°C	B
C_{(OUT_REFIO)}	Decoupling capacitor on REFIO			10	22		µF	B
V_(REFCAP)	Reference voltage to ADC (on REFCAP pin)		At T_A = 25°C	4.094	4.096	4.098	V	A
	Reference buffer output impedance				0.5	1	Ω	B
	Reference buffer temperature drift				0.6	1.5	ppm/°C	B
C_{(OUT_REFCAP)}	Decoupling capacitor on REFCAP			10	22		μF	B
	Turn-on time		C_{(OUT_REFCAP)} = 22 µF, C_{(OUT_REFIO)} = 22 µF		15		ms	B
EXTERNAL REFERENCE INPUT
V_{REFIO_EXT}	External reference voltage on REFIO (configured as input)			4.046	4.096	4.146	V	C
POWER-SUPPLY REQUIREMENTS
AVDD	Analog power-supply voltage		Analog supply	4.75	5	5.25	V	B
DVDD	Digital power-supply voltage		Digital supply range	1.65	3.3	AVDD	V	B
DVDD	Digital power-supply voltage		Digital supply range for specified performance	2.7	3.3	5.25	V	B
I_{AVDD_DYN}	Analog supply current	Dynamic, AVDD	For the ADS8678; AVDD = 5 V, f_S = maximum and internal reference		13	16	mA	A
I_{AVDD_DYN}		Dynamic, AVDD	For the ADS8674; AVDD = 5 V, f_S = maximum and internal reference		8.5	11.5	mA	A
I_{AVDD_STC}		Static	For the ADS8678; AVDD = 5 V, device not converting and internal reference		10	12	mA	A
I_{AVDD_STC}		Static	For the ADS8674; AVDD = 5 V, device not converting and internal reference		5.5	8.5	mA	A
I_STDBY		Standby	At AVDD = 5 V, device in STDBY mode and internal reference		3	4.5	mA	A
I_{PWR_DN}		Power-down	At AVDD = 5 V, device in PWR_DN		3	20	μA	B
I_{DVDD_DYN}	Digital supply current		At DVDD = 3.3 V, output = 0000h		0.5		mA	A
DIGITAL INPUTS (CMOS)
V_IH	Digital input logic levels DVDD > 2.1 V			0.7 × DVDD		DVDD + 0.3	V	A
V_IL	Digital input logic levels DVDD > 2.1 V			–0.3		0.3 × DVDD	V	A
V_IH	Digital input logic levels DVDD ≤ 2.1 V			0.8 × DVDD		DVDD + 0.3	V	A
V_IL	Digital input logic levels DVDD ≤ 2.1 V			–0.3		0.2 × DVDD	V	A
	Input leakage current				100		nA	A
	Input pin capacitance				5		pF	C
DIGITAL OUTPUTS (CMOS)
V_OH	Digital output logic levels		I_O = 500-μA source	0.8 × DVDD		DVDD	V	A
V_OL	Digital output logic levels		I_O = 500-μA sink	0		0.2 × DVDD	V	A
	Floating state leakage current		Only for SDO		1		µA	A
	Internal pin capacitance				5		pF	C
TEMPERATURE RANGE
T_A	Operating free-air temperature			–40		125	°C	B

(1) Test Levels: (A) Tested at final test. Over temperature limits are set by characterization and simulation. (B) Limits set by characterization and simulation, across temperature range. (C) Typical value only for information, provided by design simulation.

(2) Ideal input span, does not include gain or offset error.

(3) LSB = least significant bit.

(4) FSR = full-scale range.

(5) Calculated on the first nine harmonics of the input frequency.

(6) This parameter is the endpoint INL, not best-fit INL.

(7) Isolation crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel, not selected in the multiplexing sequence, and measuring its effect on the output of any selected channel.

(8) Memory crosstalk is measured by applying a full-scale sinusoidal signal up to 10 kHz to a channel that is selected in the multiplexing sequence, and measuring its effect on the output of the next selected channel for all combinations of input channels.

(9) Does not include the variation in voltage resulting from solder-shift and long-term effects.

(10) Does not include the shift in offset over time.

7.6 Timing Requirements: Serial Interface

Minimum and maximum specifications are at T_A = –40°C to 125°C. Typical specifications are at T_A = 25°C.
AVDD = 5 V, DVDD = 3 V, V_REF = 4.096 V (internal), SDO load = 20 pF, and f_SAMPLE = 500 kSPS, unless otherwise noted.

		MIN	MAX	UNIT
TIMING SPECIFICATIONS
f_S	Sampling frequency (f_CLK = max)		500	kSPS
t_S	ADC cycle time period (f_CLK = max)	2		µs
f_SCLK	Serial clock frequency (f_S = max)		17	MHz
t_SCLK	Serial clock time period (f_S = max)	59		ns
t_CONV	Conversion time		850	ns
t_{DZ_CSDO}	Delay time: CS falling to data enable		10	ns
t_{D_CKCS}	Delay time: last SCLK falling to CS rising	10		ns
t_{DZ_CSDO}	Delay time: CS rising to SDO going to 3-state	10		ns
TIMING REQUIREMENTS
t_ACQ	Acquisition time	1150		ns
t_{PH_CK}	Clock high time	0.4	0.6	t_SCLK
t_{PL_CK}	Clock low time	0.4	0.6	t_SCLK
t_{PH_CS}	CS high time	30		ns
t_{SU_CSCK}	Setup time: CS falling to SCLK falling	30		ns
t_{HT_CKDO}	Hold time: SCLK falling to (previous) data valid on SDO	10		ns
t_{SU_DOCK}	Setup time: SDO data valid to SCLK falling	25		ns
t_{SU_DICK}	Setup time: SDI data valid to SCLK falling	5		ns
t_{HT_CKDI}	Hold time: SCLK falling to (previous) data valid on SDI	5		ns
t_{SU_DSYCK}	Setup time: DAISY data valid to SCLK falling	5		ns
t_{HT_CKDSY}	Hold time: SCLK falling to (previous) data valid on DAISY	5		ns

ADS8674 ADS8678 tim_interface_sbas627.gif

Figure 1. Serial Interface Timing Diagram

7.7 Typical Characteristics

At T_A = 25°C, AVDD = 5 V, DVDD = 3 V, internal reference V_REF = 4.096 V, and f_SAMPLE = 500 kSPS, unless otherwise noted.

Figure 2. Input I-V Characteristic

Figure 4. Input Impedance Variation vs Temperature

Mean = 8192.5, sigma = 0.31, input = 0 V,
range = ±2.5 × V_REF

Figure 6. DC Histogram for Mid-Scale Inputs (±2.5 × V_REF)

Mean = 8192.5, sigma = 0.34, input = 0 V,
range = ±0.625 × V_REF

Figure 8. DC Histogram for Mid-Scale Inputs (±0.625 × V_REF)

Mean = 8192.5, sigma = 0.34, input = 0.625 × V_REF,
range = 1.25 × V_REF

Figure 10. DC Histogram for Mid-Scale Inputs
(1.25 × V_REF)

Mean = 8192.5, sigma = 0.72, input = 0 V,
range = ±0.15625 × V_REF

Figure 12. DC Histogram for Mid-Scale Inputs
(±0.15625 x V_REF)

Mean = 8192.5, sigma = 0.750.72, input = 0.15625 × V_REF,
range = 0.3125 × V_REF

Figure 14. DC Histogram for Mid-Scale Inputs
(0.3125 x V_REF)

All input ranges

Figure 16. DNL vs Temperature

Range = ±1.25 × V_REF

Figure 18. Typical INL for All Codes

Range = 2.5 × V_REF

Figure 20. Typical INL for All Codes

Range = ±0.3125 × V_REF

Figure 22. Typical INL for All Codes

Range = 0.625 × V_REF

Figure 24. Typical INL for All Codes

Range = ±2.5 × V_REF

Figure 26. INL vs Temperature (±2.5 × V_REF)

Range = ±0.625 × V_REF

Figure 28. INL vs Temperature (±0.625 × V_REF)

Range = 1.25 × V_REF

Figure 30. INL vs Temperature (1.25 × V_REF)

Range = ±0.15625 × V_REF

Figure 32. INL vs Temperature (±0.15625 × V_REF)

Range = 0.3125 × V_REF

Figure 34. INL vs Temperature (0.3125 × V_REF)

Range = ±2.5 × V_REF

Figure 36. Typical Histogram for Offset Drift

Figure 38. Gain Error vs Temperature Across Input Ranges

Range = ±2.5 × V_REF

Figure 40. Gain Error vs Temperature Across Channels

Number of points = 16k, f_IN = 1 kHz, SNR = 85.37 dB,
SINAD = 85.35, THD = –104.68 dB, SFDR = 105 dB

Figure 42. Typical FFT Plot (±2.5 × V_REF)

Number of points = 16k, f_IN = 1 kHz, SNR = 84.69 dB,
SINAD = 84.67 dB, THD = –106.41 dB, SFDR = 105 dB

Figure 44. Typical FFT Plot (±0.625 × V_REF)

Number of points = 16k, f_IN = 1 kHz, SNR = 84.62 dB,
SINAD = 84.65 dB, THD = –103.74 dB, SFDR = 105 dB

Figure 46. Typical FFT Plot (1.25 × V_REF)

Number of points = 16k, f_IN = 1 kHz, SNR = 78.09 dB,
SINAD = 78.06 dB, THD = –99.41 dB, SFDR = 105 dB

Figure 48. Typical FFT Plot (±0.15625 × V_REF)

Number of points = 16k, f_IN = 1 kHz, SNR = 78.09 dB,
SINAD = 78.05 dB, THD = –96.74 dB, SFDR = 105 dB

Figure 50. Typical FFT Plot (0.3125 × V_REF)

f_IN = 1 kHz

Figure 52. SNR vs Temperature

f_IN = 1 kHz

Figure 54. SINAD vs Temperature

f_IN = 1 kHz

Figure 56. THD vs Temperature

Figure 58. Isolation Crosstalk vs Frequency

Input = 2 × maximum input voltage

Figure 60. Isolation Crosstalk vs Frequency for
Overrange Inputs

Figure 62. AVDD Current vs Temperature for the ADS8678
(During Sampling)

Figure 64. AVDD Current vs Temperature for the ADS8674
(During Sampling)

Figure 66. AVDD Current vs Temperature
(Power Down)

Input range = ±2.5 × V_REF

Figure 3. Input Current vs Temperature

Number of samples = 1160

Figure 5. Typical Distribution of Input Impedance

Mean = 8192.5, sigma = 0.32, input = 0 V,
range = ±1.25 × V_REF

Figure 7. DC Histogram for Mid-Scale Inputs (±1.25 × V_REF)

Mean = 8192.5, sigma = 0.32, input = 1.25 × V_REF,
range = 2.5 × V_REF

Figure 9. DC Histogram for Mid-Scale Inputs (2.5 × V_REF)

Mean = 8192.5, sigma = 0.43, input = 0 V,
range = ±0.3125 × V_REF

Figure 11. DC Histogram for Mid-Scale Inputs
(±0.3125 x V_REF)

Mean = 8192.5, sigma = 0.72, input = 0.3125 × V_REF,
range = 0.625 × V_REF

Figure 13. DC Histogram for Mid-Scale Inputs
(0.625 x V_REF)

All input ranges

Figure 15. Typical DNL for All Codes

Range = ±2.5 × V_REF

Figure 17. Typical INL for All Codes

Range = ±0.625 × V_REF

Figure 19. Typical INL for All Codes

Range = 1.25 × V_REF

Figure 21. Typical INL for All Codes

Range = ±0.15625 × V_REF

Figure 23. Typical INL for All Codes

Range = 0.3125 × V_REF

Figure 25. Typical INL for All Codes

Range = ±1.25 × V_REF

Figure 27. INL vs Temperature (±1.25 × V_REF)

Range = 2.5 × V_REF

Figure 29. INL vs Temperature (2.5 × V_REF)

Range = ±0.3125 × V_REF

Figure 31. INL vs Temperature (±0.3125 × V_REF)

Range = 0.625 × V_REF

Figure 33. INL vs Temperature (0.625 × V_REF)

Figure 35. Offset Error vs
Temperature Across Input Ranges

Range = ±2.5 × V_REF

Figure 37. Offset Error vs Temperature Across Channels

Range = ±2.5 × V_REF

Figure 39. Typical Histogram for Gain Error Drift

Figure 41. Gain Error vs External Resistance (R_EXT)

Number of points = 16k, f_IN = 1 kHz, SNR = 85.11 dB,
SINAD = 85.15 dB, THD = –105.28 dB, SFDR = 105 dB

Figure 43. Typical FFT Plot (±1.25 × V_REF)

Number of points = 16k, f_IN = 1 kHz, SNR = 85.04 dB,
SINAD = 85.04 dB, THD = –106.31 dB, SFDR = 105 dB

Figure 45. Typical FFT Plot (2.5 × V_REF)

Number of points = 16k, f_IN = 1 kHz, SNR = 82.59 dB,
SINAD = 82.56 dB, THD = –102.41 dB, SFDR = 105 dB

Figure 47. Typical FFT Plot (±0.3125 × V_REF)

Number of points = 16k, f_IN = 1 kHz, SNR = 82.59 dB,
SINAD = 82.55 dB, THD = –99.74 dB, SFDR = 105 dB

Figure 49. Typical FFT Plot (0.625 × V_REF)

Figure 51. SNR vs Input Frequency

Figure 53. SINAD vs Input Frequency

Figure 55. THD vs Input Frequency

Figure 57. Memory Crosstalk vs Frequency

Input = 2 × maximum input voltage

Figure 59. Memory Crosstalk vs Frequency for
Overrange Inputs

Figure 61. AVDD Current vs Temperature for the ADS8678
(f_S = 500 kSPS)

Figure 63. AVDD Current vs Temperature for the ADS8674
(f_S = 500 kSPS)

Figure 65. AVDD Current vs Temperature
(STANDBY)