JAJSD74E February   2016  – August 2022 ADS8681 , ADS8685 , ADS8689

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements: Conversion Cycle
    7. 6.7  Timing Requirements: Asynchronous Reset
    8. 6.8  Timing Requirements: SPI-Compatible Serial Interface
    9. 6.9  Timing Requirements: Source-Synchronous Serial Interface (External Clock)
    10. 6.10 Timing Requirements: Source-Synchronous Serial Interface (Internal Clock)
    11. 6.11 Timing Diagrams
    12. 6.12 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input Structure
      2. 7.3.2 Analog Input Impedance
      3. 7.3.3 Input Protection Circuit
      4. 7.3.4 Programmable Gain Amplifier (PGA)
      5. 7.3.5 Second-Order, Low-Pass Filter (LPF)
      6. 7.3.6 ADC Driver
      7. 7.3.7 Reference
        1. 7.3.7.1 Internal Reference
        2. 7.3.7.2 External Reference
      8. 7.3.8 ADC Transfer Function
      9. 7.3.9 Alarm Features
        1. 7.3.9.1 Input Alarm
        2. 7.3.9.2 AVDD Alarm
    4. 7.4 Device Functional Modes
      1. 7.4.1 Host-to-Device Connection Topologies
        1. 7.4.1.1 Single Device: All multiSPI Options
        2. 7.4.1.2 Single Device: Standard SPI Interface
        3. 7.4.1.3 Multiple Devices: Daisy-Chain Topology
      2. 7.4.2 Device Operational Modes
        1. 7.4.2.1 RESET State
        2. 7.4.2.2 ACQ State
        3. 7.4.2.3 CONV State
    5. 7.5 Programming
      1. 7.5.1 Data Transfer Frame
      2. 7.5.2 Input Command Word and Register Write Operation
      3. 7.5.3 Output Data Word
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols with a Single SDO-x
          2. 7.5.4.2.2 Legacy, SPI-Compatible (SYS-xy-S) Protocols With Dual SDO-x
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options
            2. 7.5.4.2.3.2 Output Bus Width Options
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 DEVICE_ID_REG Register (address = 00h)
        2. 7.6.1.2 RST_PWRCTL_REG Register (address = 04h)
        3. 7.6.1.3 SDI_CTL_REG Register (address = 08h)
        4. 7.6.1.4 SDO_CTL_REG Register (address = 0Ch)
        5. 7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)
        6. 7.6.1.6 RANGE_SEL_REG Register (address = 14h)
        7. 7.6.1.7 ALARM_REG Register (address = 20h)
        8. 7.6.1.8 ALARM_H_TH_REG Register (address = 24h)
        9. 7.6.1.9 ALARM_L_TH_REG Register (address = 28h)
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Decoupling
      2. 8.3.2 Power Saving
        1. 8.3.2.1 NAP Mode
        2. 8.3.2.2 Power-Down (PD) Mode
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.1.5 DATAOUT_CTL_REG Register (address = 10h)

This register controls the data output by the device.

Figure 7-40 DATAOUT_CTL_REG Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
R-0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DEVICE_
ADDR_ INCL		 VDD_ACTIVE_
ALARM_INCL[1:0]		 IN_ACTIVE_
ALARM_INCL[1:0]		 Reserved RANGE_ INCL Reserved PAR_EN DATA_VAL
[2:0]
R-0b R/W-0b R/W-0b R/W-0b R-0b R/W-0b R-0000b R/W-<0>b R/W-000b
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset; -0, -1 = Condition after application reset;
-<0>, -<1> = Condition after power-on reset
Address for bits 7-0 = 10h Address for bits 15-8 = 11h Address for bits 23-16 = 12h Address for bits 31-24 = 13h
Table 7-15 DATAOUT_CTL_REG Register Field Descriptions
Bit Field Type Reset Description
31-16 Reserved R 0000h Reserved. Reads return 0000h.
15 Reserved R 0b Reserved. Reads return 0b.
14 DEVICE_ADDR_INCL R/W 0b Control to include the 4-bit DEVICE_ADDR register value in the SDO-x output bit stream.
0b = Do not include the register value
1b = Include the register value
13-12 VDD_ACTIVE_ALARM_INCL[1:0] R/W 00b Control to include the active VDD ALARM flags in the SDO-x output bit stream.
00b = Do not include
01b = Include ACTIVE_VDD_H_FLAG
10b = Include ACTIVE_VDD_L_FLAG
11b = Include both flags
11-10 IN_ACTIVE_ALARM_INCL[1:0] R/W 00b Control to include the active input ALARM flags in the SDO-x output bit stream.
00b = Do not include
01b = Include ACTIVE_IN_H_FLAG
10b = Include ACTIVE_IN_L_FLAG
11b = Include both flags
9 Reserved R 0b Reserved. Reads return 0h.
8 RANGE_INCL R/W 0b Control to include the 4-bit input range setting in the SDO-x output bit stream.
0b = Do not include the range configuration register value
1b = Include the range configuration register value
7-4 Reserved R 0000b Reserved. Reads return 0000b.
3 PAR_EN(1) R/W 0b 0b = Output data does not contain parity information
1b = Two parity bits (ADC output and output data frame) are appended to the LSBs of the output data
The ADC output parity bit reflects an even parity for the ADC output bits only.
The output data frame parity bit reflects an even parity signature for the entire output data frame, including the ADC output bits and any internal flags or register settings. The ADC output parity bit is not included in the frame parity bit computation.
2-0 DATA_VAL[2:0] R/W 000b These bits control the data value output by the converter.
0xxb = Value output is the conversion data
100b = Value output is all 0's
101b = Value output is all 1's
110b = Value output is alternating 0's and 1's
111b = Value output is alternating 00's and 11's
(1) Setting this bit increases the length of the output data by two bits.