JAJSEC1C November   2019  – July 2020 ADS8686S

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams: Universal
    9. 6.9  Timing Diagrams: Parallel Data Read
    10. 6.10 Timing Diagrams: Serial Data Read
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Programmable, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer
      8. 7.3.8  Digital Filter and Noise
      9. 7.3.9  Reference
        1. 7.3.9.1 Internal Reference
        2. 7.3.9.2 External Reference
        3. 7.3.9.3 Supplying One VREF to Multiple Devices
      10. 7.3.10 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RESET (Input)
        3. 7.4.1.3  SEQEN (Input)
        4. 7.4.1.4  HW_RANGESEL[1:0] (Input)
        5. 7.4.1.5  SER/BYTE/PAR (Input)
        6. 7.4.1.6  DB[3:0] (Input/Output)
        7. 7.4.1.7  DB4/SER1W (Input/Output)
        8. 7.4.1.8  DB5/CRCEN (Input/Output)
        9. 7.4.1.9  DB[7:6] (Input/Output)
        10. 7.4.1.10 DB8 (Input/Output)
        11. 7.4.1.11 DB9/BYTESEL (Input/Output)
        12. 7.4.1.12 DB10/SDI (Input/Output)
        13. 7.4.1.13 DB11/SDOB (Input/Output)
        14. 7.4.1.14 DB12/SDOA (Input/Output)
        15. 7.4.1.15 DB13/OS0 (Input/Output)
        16. 7.4.1.16 DB14/OS1 (Input/Output)
        17. 7.4.1.17 DB15/OS2 (Input/Output)
        18. 7.4.1.18 WR/BURST (Input)
        19. 7.4.1.19 SCLK/RD (Input)
        20. 7.4.1.20 CS (Input)
        21. 7.4.1.21 CHSEL[2:0] (Input)
        22. 7.4.1.22 BUSY (Output)
        23. 7.4.1.23 CONVST (Input)
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Shutdown Mode
        2. 7.4.2.2 Operation Mode
          1. 7.4.2.2.1 Hardware Mode
          2. 7.4.2.2.2 Software Mode
        3. 7.4.2.3 Reset Functionality
        4. 7.4.2.4 Channel Selection
          1. 7.4.2.4.1 Hardware Mode Channel Selection
          2. 7.4.2.4.2 Software Mode Channel Selection
        5. 7.4.2.5 Sequencer
          1. 7.4.2.5.1 Hardware Mode Sequencer
          2. 7.4.2.5.2 Software Mode Sequencer
        6. 7.4.2.6 Burst Sequencer
          1. 7.4.2.6.1 Hardware Mode Burst Sequencer
          2. 7.4.2.6.2 Software Mode Burst Sequencer
        7. 7.4.2.7 Diagnostics
          1. 7.4.2.7.1 Analog Diagnosis
          2. 7.4.2.7.2 Interface Diagnosis: SELF TEST and CRC
    5. 7.5 Programming
      1. 7.5.1 Parallel Interface
        1. 7.5.1.1 Reading Conversion Results
        2. 7.5.1.2 Writing Register Data
        3. 7.5.1.3 Reading Register Data
      2. 7.5.2 Parallel Byte Interface
        1. 7.5.2.1 Reading Conversion Results
        2. 7.5.2.2 Writing Register Data
        3. 7.5.2.3 Reading Register Data
      3. 7.5.3 Serial Interface
        1. 7.5.3.1 Reading Conversion Results
        2. 7.5.3.2 Writing Register Data
        3. 7.5.3.3 Reading Register Data
    6. 7.6 Register Maps
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 8x2 Channel Data Acquisition System (DAQ) for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Input Protection for Electrical Overstress
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報
7.4.2.2.1 Hardware Mode

The device enters hardware mode if the HW_RNGSEL[1:0] pins are set to either 01, 10, or 11 at the time of a full reset. In hardware mode, the device operates with restricted functionality. All device functionality is configured through the pin control. The logic levels of the following signals at a full reset configure the functionality of the ADS8686S: CRC, BURST, SEQEN, SER/BYTE/ PAR, DB9/BYESEL, DB8, and OSx. Table 7-5 provides a summary of the signals that are latched by the device on the release of a full reset. After the device is configured, a full reset through the RESET pin is required to exit the configuration and set up an alternate configuration. The data communication interface selected also dictates the functionality available in hardware mode. Table 7-6 provides a full list of the functionality available in hardware parallel, byte, or serial mode.

Table 7-5 Summary of Hardware Pin Behavior
SIGNAL LATCHED AT FULL RESET READ AT RESET READ WHEN BUSY EDGE DRIVEN
HW
MODE		 SW
MODE		 HW
MODE		 SW
MODE		 HW
MODE		 SW
MODE		 HW
MODE		 SW
MODE
REFSEL Yes Yes
SEQEN Yes
HW_RNGSELx
(range change)		 Yes Yes Yes
HW_RNGSELx
(HW or SW mode)		 Yes Yes
CRCEN Yes No
OSx Yes No
BURST Yes No
CHSELx Yes Yes
SER1W Yes Yes
SER/BYTE/ PAR Yes Yes
DB9/BYTESEL Yes Yes
Table 7-6 Pin Functionality Overview
PIN NAME OPERATION MODE
SOFTWARE, HW_RNGSELx = 00 HARDWARE, HW_RNGSELx ≠ 00
SERIAL, SER/BYTE/ PAR = 1, DB9/BYTESEL = 0 PARALLEL BYTE, SER/BYTE/ PAR = 1, DB9/BYTESEL = 1 PARALLEL, SER/BYTE/ PAR = 0 SERIAL, SER/BYTE/ PAR = 1, DB9/BYTESEL = 0 PARALLEL BYTE, SER/BYTE/ PAR = 1, DB9/BYTESEL = 1 PARALLEL, SER/BYTE/ PAR = 0
CHSELx No function, connect to DGND No function, connect to DGND No function, connect to DGND CHSELx CHSELx CHSELx
SCLK/ RD SCLK RD RD SCLK RD RD
WR/BURST Connect to DGND WR WR BURST BURST BURST
DB[15:13]/OS[0:2] Connect to DGND Connect to DGND DB15 to DB13 OSx Connect to DGND DB15 to DB13
DB12/SDOA SDOA Connect to DGND DB12 SDOA Connect to DGND DB12
DB11/SDOB SDOB, leave floating for serial 1-wire mode Connect to DGND DB11 SDOB Connect to DGND DB11
DB10/SDI SDI Connect to DGND DB10 Connect to DGND Connect to DGND DB10
DB9/BYTESEL Connect to DGND Connect to DVDD DB9 Connect to DGND Connect to DVDD DB9
DB8 to DB6,
DB3 to DB0		 Connect to DGND DB8 to DB6,
DB3 to DB0		 DB8 to DB6,
DB3 to DB0		 Connect to DGND DB8 to DB6,
DB3 to DB0		 DB8 to DB6,
DB3 to DB0
DB5/CRCEN Connect to DGND DB5 DB5 CRCEN DB5 DB5
DB4/ SER1W SER1W DB4 DB4 SER1W DB4 DB4
HW_RNGSELx Connect to DGND Connect to DGND Connect to DGND Configure analog input range Configure analog input range Configure analog input range
SEQEN Connect to DGND Connect to DGND Connect to DGND SEQEN SEQEN SEQEN
REFSEL REFSEL REFSEL REFSEL REFSEL REFSEL REFSEL

In hardware mode, the CHSELx and HW_RNGSELx control signals can change their state during device operation and have an immediate effect on the device configuration.

The CHSELx pins are read at reset to determine the first analog input channel pair to be acquired for conversion. In the sequencer mode of operation, the CHSELx pins configure the settings for the sequencer. See the Section 7.4.2.5 section for additional details. The CHSELx pin status must be kept constant during the ADC conversion process (that is, between the CONVST rising edge and the BUSY falling edge). The status of the CHSELx pins is read during this time to select the next channel pair for conversion or to modify the hardware sequencer setting.

The HW_RNGSELx signals program the analog input range. The selected input range is applied to all 16 analog input channels. A logic change on these pins has an immediate effect on the analog input range. Allow for a typical settling time of 120 µs, in addition to the normal acquisition time requirement after the range change. The recommended practice is to hardwire the range select pins according to the desired input range for the system signals.