JAJSEC1C November 2019 – July 2020 ADS8686S
PRODUCTION DATA
The ADS8686S supports on-chip register access in software mode. A single register write command is performed by a 16-bit access through the parallel byte bus (DB7 to DB0), CS, and WR signals. The 16-bit data to be fed on the DB[7:0] pins is determined by the register to be addressed and the device settings needed for the application. See the Section 7.6 section to determine the register content. Pull the CS pin low to take the DB[7:0] pins out of high-impedance state. Pull the WR pin low to configure the DB[7:0] pins as digital inputs. The host drives the DB[7:0] pins with the MSB of data to program the on-chip register. When the MSB is programmed, pull the WR pin high. Repeat the same procedure to drive the LSB of the data to program on-chip register. Data are latched into the device on the rising edge of the second WR pulse. Any additional byte accesses are ignored. Pull the CS pin high to terminate the resister write operation. Figure 7-27 shows the parallel register write timing diagram.