JAJSEC1C November   2019  – July 2020 ADS8686S

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics
    6. 6.6  Timing Requirements
    7. 6.7  Switching Characteristics
    8. 6.8  Timing Diagrams: Universal
    9. 6.9  Timing Diagrams: Parallel Data Read
    10. 6.10 Timing Diagrams: Serial Data Read
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Analog Inputs
      2. 7.3.2  Analog Input Impedance
      3. 7.3.3  Input Clamp Protection Circuit
      4. 7.3.4  Programmable Gain Amplifier (PGA)
      5. 7.3.5  Second-Order, Programmable, Low-Pass Filter (LPF)
      6. 7.3.6  ADC Driver
      7. 7.3.7  Multiplexer
      8. 7.3.8  Digital Filter and Noise
      9. 7.3.9  Reference
        1. 7.3.9.1 Internal Reference
        2. 7.3.9.2 External Reference
        3. 7.3.9.3 Supplying One VREF to Multiple Devices
      10. 7.3.10 ADC Transfer Function
    4. 7.4 Device Functional Modes
      1. 7.4.1 Device Interface: Pin Description
        1. 7.4.1.1  REFSEL (Input)
        2. 7.4.1.2  RESET (Input)
        3. 7.4.1.3  SEQEN (Input)
        4. 7.4.1.4  HW_RANGESEL[1:0] (Input)
        5. 7.4.1.5  SER/BYTE/PAR (Input)
        6. 7.4.1.6  DB[3:0] (Input/Output)
        7. 7.4.1.7  DB4/SER1W (Input/Output)
        8. 7.4.1.8  DB5/CRCEN (Input/Output)
        9. 7.4.1.9  DB[7:6] (Input/Output)
        10. 7.4.1.10 DB8 (Input/Output)
        11. 7.4.1.11 DB9/BYTESEL (Input/Output)
        12. 7.4.1.12 DB10/SDI (Input/Output)
        13. 7.4.1.13 DB11/SDOB (Input/Output)
        14. 7.4.1.14 DB12/SDOA (Input/Output)
        15. 7.4.1.15 DB13/OS0 (Input/Output)
        16. 7.4.1.16 DB14/OS1 (Input/Output)
        17. 7.4.1.17 DB15/OS2 (Input/Output)
        18. 7.4.1.18 WR/BURST (Input)
        19. 7.4.1.19 SCLK/RD (Input)
        20. 7.4.1.20 CS (Input)
        21. 7.4.1.21 CHSEL[2:0] (Input)
        22. 7.4.1.22 BUSY (Output)
        23. 7.4.1.23 CONVST (Input)
      2. 7.4.2 Device Modes of Operation
        1. 7.4.2.1 Shutdown Mode
        2. 7.4.2.2 Operation Mode
          1. 7.4.2.2.1 Hardware Mode
          2. 7.4.2.2.2 Software Mode
        3. 7.4.2.3 Reset Functionality
        4. 7.4.2.4 Channel Selection
          1. 7.4.2.4.1 Hardware Mode Channel Selection
          2. 7.4.2.4.2 Software Mode Channel Selection
        5. 7.4.2.5 Sequencer
          1. 7.4.2.5.1 Hardware Mode Sequencer
          2. 7.4.2.5.2 Software Mode Sequencer
        6. 7.4.2.6 Burst Sequencer
          1. 7.4.2.6.1 Hardware Mode Burst Sequencer
          2. 7.4.2.6.2 Software Mode Burst Sequencer
        7. 7.4.2.7 Diagnostics
          1. 7.4.2.7.1 Analog Diagnosis
          2. 7.4.2.7.2 Interface Diagnosis: SELF TEST and CRC
    5. 7.5 Programming
      1. 7.5.1 Parallel Interface
        1. 7.5.1.1 Reading Conversion Results
        2. 7.5.1.2 Writing Register Data
        3. 7.5.1.3 Reading Register Data
      2. 7.5.2 Parallel Byte Interface
        1. 7.5.2.1 Reading Conversion Results
        2. 7.5.2.2 Writing Register Data
        3. 7.5.2.3 Reading Register Data
      3. 7.5.3 Serial Interface
        1. 7.5.3.1 Reading Conversion Results
        2. 7.5.3.2 Writing Register Data
        3. 7.5.3.3 Reading Register Data
    6. 7.6 Register Maps
      1. 7.6.1 Page1 Registers
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 8x2 Channel Data Acquisition System (DAQ) for Power Automation
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curve
      2. 8.2.2 Input Protection for Electrical Overstress
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supplies
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Examples
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Development Support
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 Receiving Notification of Documentation Updates
    4. 11.4 サポート・リソース
    5. 11.5 Trademarks
    6. 11.6 Electrostatic Discharge Caution
    7. 11.7 Glossary

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.3.8 Digital Filter and Noise

The ADS8686S features an optional digital second-order sinc filter that can be used in slower throughput applications requiring lower noise and higher dynamic range. As explained in Table 7-3, the oversampling ratio of the digital filter is determined by the configuration of the OS[2:0] pins in hardware mode or through the OS bits programming in software mode. When enabled, the oversampling is applicable for all channels. The overall throughput of the ADC decreases proportionally with the increase to the oversampling ratio. When the oversampling ratio increases, there is a proportional improvement in the SNR performance and decrease in the bandwidth of the input signal.

In oversampling mode, the ADC takes the first sample for each channel at the rising edge of the CONVST signal. After converting the first sample, the subsequent samples are taken by an internally generated sampling control signal. The samples are then averaged to reduce the noise of the signal chain as well as to improve the SNR of the ADC. The final output is also decimated to provide a 16-bit output for each channel.

If oversampling is enabled with the sequencer in burst mode, the extra samples are gathered for a given channel before the sequencer moves on to the next channel.

Table 7-3 Oversampling Bit Decoding
OSx PINS,
OS BITS		 OSR LPF OPTION TYPICAL SNR (dB) −3-dB BANDWIDTH (kHz)
±2.5-V RANGE ±3-V RANGE ±5-V RANGE ±6-V RANGE ±10-V RANGE ±12-V RANGE ±10-V RANGE
000 No OSR LPF 1 86.99 87.32 89.55 89.69 90.69 90.53 39.4
001 2 LPF 1 87.6 87.89 90.25 90.4 91.53 91.35 39.4
010 4 LPF 1 88.04 88.36 90.89 91.01 92.37 92.17 37.5
011 8 LPF 1 88.74 89.07 91.65 97.79 93.29 93.08 32.0
100 16 LPF 1 89.97 90.28 92.76 92.92 94.4 94.21 22.4
101 32 LPF 1 91.98 92.21 94.33 94.45 95.65 95.53 12.9
110 64 LPF 1 93.61 93.95 95.68 95.83 96.8 96.69 6.8
111 128 LPF 1 95.53 95.9 97.27 97.42 97.97 98.01 3.4
000 No OSR LPF 2 89.05 89.35 90.98 91.11 91.92 91.85 15.4
001 2 LPF 2 89.94 90.18 91.91 92.01 92.94 92.84 15.4
010 4 LPF 2 90.4 90.65 92.62 92.73 93.82 93.72 15.3
011 8 LPF 2 90.81 91.08 93.2 93.31 94.53 94.42 14.8
100 16 LPF 2 91.39 91.7 93.82 93.95 95.19 95.07 13.3
101 32 LPF 2 92.74 92.96 94.84 94.95 95.99 95.87 10.1
110 64 LPF 2 93.85 94.2 95.91 96.04 96.88 96.85 6.2
111 128 LPF 2 95.62 95.94 97.28 97.47 98.04 98.02 3.4
000 No OSR LPF 3 77.29 77.33 81.12 81.25 84.33 83.58 399.9
001 2 LPF 3 80.11 80.34 83.79 83.95 86.77 86.26 210.3
010 4 LPF 3 82.97 83.24 86.52 86.67 89.25 88.87 108.8
011 8 LPF 3 85.82 86.1 89.14 89.31 91.58 91.28 55.0
100 16 LPF 3 88.53 88.81 91.56 91.73 93.59 93.38 27.6
101 32 LPF 3 91.26 91.5 93.78 93.89 95.28 95.12 13.8
110 64 LPF 3 93.29 93.64 95.49 95.6 96.62 96.52 6.9
111 128 LPF 3 95.46 95.79 97.1 97.27 97.94 97.89 3.5