JAJSCN8A November 2016 – June 2017 ADS8900B , ADS8902B , ADS8904B
PRODUCTION DATA.
NOTE
Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.
The two primary circuits required to maximize the performance of a high-precision, successive approximation register (SAR), analog-to-digital converter (ADC) are the input driver and the reference driver circuits. This section presents general principles for designing these circuits, followed by an application circuit designed using the ADS890xB.
The external reference source must provide low-drift and very accurate voltage at the REFIN pin of the ADS890xB. The output broadband noise of most references can be in the order of a few hundred μVRMS. Therefore, to prevent any degradation in the noise performance of the ADC, appropriately filter the output of the voltage reference by using a low-pass filter with a cutoff frequency of a few hundred hertz.
The internal reference buffer of the ADS890xB provides the dynamic load posed on the REFBUFOUT pin during the conversion process. Decouple the REFBUFOUT pin with the REFM pin using the recommended CREFBUF and RESR. See the Layout section for layout recommendations.
The input driver circuit for a high-precision ADC mainly consists of two parts: a driving amplifier and a charge kickback filter. The amplifier is used for signal conditioning of the input signal and the low output impedance of the amplifier provides a buffer between the signal source and the switched capacitor inputs of the ADC. The charge kickback filter helps attenuate the sampling charge injection from the switched-capacitor input stage of the ADC, and band-limits the wideband noise contributed by the front-end circuit. Careful design of the front-end circuit is critical to meet the linearity and noise performance of the ADS890xB.
The charge-kickback filter is an RC filter at the input pins of the ADC that filters the broadband noise from the front-end drive circuitry, and attenuates the sampling charge injection from the switched-capacitor input stage of the ADC. A filter capacitor, CFLT, is connected from each input pin of the ADC to the ground (as shown in Figure 104). This capacitor helps reduce the sampling charge injection and provides a charge bucket to quickly charge the internal sample-and-hold capacitors during the acquisition process. Generally, the value of this capacitor must be at least 20 times the specified value of the ADC sampling capacitance. For the ADS890xB, the input sampling capacitance is equal to 60 pF; therefore, for optimal performance, keep CFLT greater than 1.2 nF. This capacitor must be a COG- or NPO-type. The type of dielectric used in COG or NPO ceramic capacitors provides the most stable electrical properties over voltage, frequency, and temperature changes.
Driving capacitive loads can degrade the phase margin of the input amplifier, thus making the amplifier marginally unstable. To avoid amplifier stability issues, series isolation resistors (RFLT) are used at the output of the amplifiers. A higher value of RFLT helps with amplifier stability, but adds distortion as a result of interactions with the nonlinear input impedance of the ADC. Distortion increases with source impedance, input signal frequency, and input signal amplitude. Therefore, the selection of RFLT requires balancing the stability of the driver amplifier and distortion performance of the design. Always verify the stability and settling behavior of the driving amplifier and charge-kickback filter by TINA-TI™ SPICE simulation. Keep the tolerance of the selected resistors less than 1% to keep the inputs balanced.
Selection criteria for the input amplifiers is highly dependent on the input signal type, as well as the performance goals, of the data acquisition system. Some key amplifier specifications to consider when selecting an appropriate amplifier to drive the inputs of the ADC are:
where
For this example, the design parameters are listed in Table 21.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
ADC sample rate | Maximum-specified throughput |
Input signal | 2-kHz input, 4.5-VPP fully differential |
Noise performance, SNR | > 101-dB, |
Distortion, THD | < –120-dB |
Linearity, INL | < ±2-ppm |
Reference | 4.5 V |
Power supply | < 5.5-V analog, 3.3-V I/O |
The application circuit is illustrated in Figure 105. For simplicity, power-supply decoupling capacitors are not shown in these circuit diagrams; see the Power-Supply Recommendations section for suggested guidelines.
The reference voltage of 4.5 V is generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz.
Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The low-power OPA2625 (a high-bandwidth, low-distortion, high-precision amplifier in an inverting gain configuration) as an input driver provides exceptional ac performance because of its extremely low-distortion and high-bandwidth specifications. The distortion resulting from variation in the common-mode signal is eliminated by using the OPA2625 in an inverting gain configuration. To exercise the complete dynamic range of the device, the common-mode voltage at the ADS890xB inputs is established at a value of 2.25 V (4.5 V / 2) by using the noninverting pins of the OPA2625 amplifiers. In addition, the components of the charge kickback filter keep the noise from the front-end circuit low without adding distortion to the input signal.
For a complete schematic, see the ADS8900BEVM-PDK user's guide located in the ADS8900B SAR Analog to Digital Converter Evaluation Module web folder at www.ti.com.
The same circuit is used in reference design TIPD211, a step-by-step process to design a 20-Bit, 1-MSPS, 4-Ch Small Form Factor Design for Test and Measurement Applications using four ADS8900B SAR ADCs, four OPA2625 precision amplifiers and one REF5050 precision reference.
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For step-by-step design procedure, circuit schematics, bill of materials, PCB files, simulation results, and test results, refer to TI Precision Design TIPD211, 18-Bit, 1-MSPS, 4-Ch Small Form Factor Design for Test and Measurement Applications (TIDUBW7). |
18-bit NMC DNL, ±1.5-ppm INL |
fIN = 2 kHz, 101.8-dB SNR, –122-dB THD |
fIN = 2 kHz, 101.8-dB SNR, –122-dB THD |
fIN = 2 kHz, 101.8-dB SNR, –122-dB THD |
For this example, the design parameters are listed in Table 22.
DESIGN PARAMETER | EXAMPLE VALUE |
---|---|
ADC sample rate | Maximum-specified throughput |
Input signal | 2-kHz input, ±4.5-VPP fully differential and ±4.5-VPP single-ended bipolar signal |
Noise performance, SNR | > 101-dB |
Distortion, THD | < –125-dB |
Linearity, INL | < ±2-ppm |
Reference | 4.5 V |
Power supply | < 5.4-V analog, 3.3-V I/O |
The application circuits are shown in Figure 110 and Figure 111. In both applications, the input signal is processed through a high-bandwidth, low-distortion, fully-differential amplifier (FDA) designed in a gain of 1 V/V and a low-pass RC filter before going to the ADC.
The reference voltage of 4.5 V generated by the high-precision, low-noise REF5045 circuit. The output broadband noise of the reference is heavily filtered by a low-pass filter with a 3-dB cutoff frequency of 16 Hz.
Generally, the distortion from the input driver must be at least 10 dB less than the ADC distortion. The distortion resulting from variation in the common-mode signal is eliminated by using the FDA in an inverting gain configuration that establishes a fixed common-mode level for the circuit. This configuration also eliminates the requirement of a rail-to-rail swing at the amplifier input. Therefore, these circuits use the low-power THS4551 as an input driver that provides exceptional ac performance because of its extremely low-distortion and high bandwidth specifications. In addition, the components of the charge kickback filter keep the noise from the front-end circuit low without adding distortion to the input signal.
The circuit in Figure 110 shows a fully-differential data acquisition (DAQ) block optimized for low distortion and noise using the THS4551 and ADS890xB. This front-end circuit configuration requires a differential signal at the input of the FDA and provides a differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4551 (not shown in Figure 110). To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
The circuit in Figure 111 shows a single-ended to differential DAQ block optimized for low distortion and noise using the THS4551 and the ADS890xB. This front-end circuit configuration requires a single-ended bipolar signal at the input of the FDA and provides a fully-differential output to drive the ADC inputs. The common-mode voltage of the input signal provided to the ADC is set by the VOCM pin of the THS4551 (not shown in Figure 111). To use the complete dynamic range of the ADC, VOCM can be set to VREF / 2 by using a simple resistive divider.
20-bit NMC DNL, ±1.5-ppm INL |
20-bit NMC DNL, ±1.5-ppm INL |
fIN = 2 kHz, 102.1-dB SNR, –131.5-dB THD |