JAJSCA2B June   2016  – January 2018 ADS8910B , ADS8912B , ADS8914B

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      ADS89xxB内蔵の機能によりシステムを簡単に設計
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 LDO Module
      2. 7.3.2 Reference Buffer Module
      3. 7.3.3 Converter Module
        1. 7.3.3.1 Sample-and-Hold Circuit
        2. 7.3.3.2 Internal Oscillator
        3. 7.3.3.3 ADC Transfer Function
      4. 7.3.4 Interface Module
    4. 7.4 Device Functional Modes
      1. 7.4.1 RST State
      2. 7.4.2 ACQ State
      3. 7.4.3 CNV State
    5. 7.5 Programming
      1. 7.5.1 Output Data Word
      2. 7.5.2 Data Transfer Frame
      3. 7.5.3 Interleaving Conversion Cycles and Data Transfer Frames
      4. 7.5.4 Data Transfer Protocols
        1. 7.5.4.1 Protocols for Configuring the Device
        2. 7.5.4.2 Protocols for Reading From the Device
          1. 7.5.4.2.1 Legacy, SPI-Compatible (SYS-xy-S) Protocols
          2. 7.5.4.2.2 SPI-Compatible Protocols with Bus Width Options
          3. 7.5.4.2.3 Source-Synchronous (SRC) Protocols
            1. 7.5.4.2.3.1 Output Clock Source Options with SRC Protocols
            2. 7.5.4.2.3.2 Bus Width Options With SRC Protocols
            3. 7.5.4.2.3.3 Output Data Rate Options With SRC Protocols
      5. 7.5.5 Device Setup
        1. 7.5.5.1 Single Device: All multiSPI Options
        2. 7.5.5.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.5.5.3 Multiple Devices: Daisy-Chain Topology
        4. 7.5.5.4 Multiple Devices: Star Topology
    6. 7.6 Register Maps
      1. 7.6.1 Device Configuration and Register Maps
        1. 7.6.1.1 PD_CNTL Register (address = 04h) [reset = 00h]
          1. Table 11. PD_CNTL Register Field Descriptions
        2. 7.6.1.2 SDI_CNTL Register (address = 008h) [reset = 00h]
          1. Table 12. SDI_CNTL Register Field Descriptions
        3. 7.6.1.3 SDO_CNTL Register (address = 0Ch) [reset = 00h]
          1. Table 13. SDO_CNTL Register Field Descriptions
        4. 7.6.1.4 DATA_CNTL Register (address = 010h) [reset = 00h]
          1. Table 14. DATA_CNTL Register Field Descriptions
        5. 7.6.1.5 PATN_LSB Register (address = 014h) [reset = 00h]
          1. Table 15. PATN_LSB Register Field Descriptions
        6. 7.6.1.6 PATN_MID Register (address = 015h) [reset = 00h]
          1. Table 16. PATN_MID Register Field Descriptions
        7. 7.6.1.7 PATN_MSB Register (address = 016h) [reset = 00h]
          1. Table 17. PATN_MSB Register Field Descriptions
        8. 7.6.1.8 OFST_CAL Register (address = 020h) [reset = 00h]
          1. Table 18. OFST_CAL Register Field Descriptions
        9. 7.6.1.9 REF_MRG Register (address = 030h) [reset = 00h]
          1. Table 19. REF_MRG Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Reference Driver
      2. 8.1.2 ADC Input Driver
        1. 8.1.2.1 Charge-Kickback Filter
        2. 8.1.2.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Data Acquisition (DAQ) Circuit for Lowest Distortion and Noise Performance With Differential Input
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Curves
      2. 8.2.2 DAQ Circuit With FDA Input Driver and Single-Ended or Differential Input
      3. 8.2.3 Design Requirements
      4. 8.2.4 Detailed Design Procedure
      5. 8.2.5 Application Curves
  9. 9 Power-Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 ドキュメントのサポート
      1. 11.1.1 関連資料
    2. 11.2 関連リンク
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.5.4.2.3.3 Output Data Rate Options With SRC Protocols

The device provides an option to transfer the data to the host controller at a single data rate (default, SDR) or at a double data rate (DDR). Set the DATA_RATE bit in the SDO_CNTL register to select the data transfer rate.

In SDR mode (DATA_RATE = 0b), the RVS pin toggles from low to high, and the output data bits are launched on the SDO pins on the output clock rising edge.

In DDR mode (DTA_RATE = 1b), the RVS pin toggles (from low-to-high or high-to-low), and the output data bits are launched on the SDO pins on every output clock edge, starting with the first rising edge.

The device supports all 24 combinations of output clock source, bus width, and output data rate, as shown in Table 9.

Table 9. SRC Protocol Combinations

PROTOCOL OUTPUT CLOCK SOURCE BUS WIDTH OUTPUT DATA RATE SDI_CNTL SDO_CNTL #OUTPUT CLOCK
(Optimal Read Frame)		 TIMING DIAGRAM
SRC-EXT-SS SCLK(1) Single SDR 00h, 01h,
02h, or 03h(2) 		03h 9 Figure 73
SRC-INT-SS INTCLK(3) Single SDR 43h 9 Figure 74
SRC-IB2-SS INTCLK / 2(3) Single SDR 83h 9
SRC-IB4-SS INTCLK / 4(3) Single SDR C3h 9
SRC-EXT-DS SCLK(1) Dual SDR 0Bh 9 Figure 77
SRC-INT-DS INTCLK(3) Dual SDR 4Bh 9 Figure 78
SRC-IB2-DS INTCLK / 2(3) Dual SDR 8Bh 9
SRC-IB4-DS INTCLK / 4(3) Dual SDR CBh 9
SRC-EXT-QS SCLK(1) Quad SDR 0Fh 5 Figure 81
SRC-INT-QS INTCLK(3) Quad SDR 4Fh 5 Figure 82
SRC-IB2-QS INTCLK / 2(3) Quad SDR 8Fh 5
SRC-IB4-QS INTCLK / 4(3) Quad SDR CFh 5
SRC-EXT-SD SCLK(1) Single DDR 13h 9 Figure 75
SRC-INT-SD INTCLK(3) Single DDR 53h 9 Figure 76
SRC-IB2-SD INTCLK / 2(3) Single DDR 93h 9
SRC-IB4-SD INTCLK / 4(3) Single DDR D3h 9
SRC-EXT-DD SCLK(1) Dual DDR 1Bh 5 Figure 79
SRC-INT-DD INTCLK(3) Dual DDR 5Bh 5 Figure 80
SRC-IB2-DD INTCLK / 2(3) Dual DDR 9Bh 5
SRC-IB4-DD INTCLK / 4(3) Dual DDR DBh 5
SRC-EXT-QD SCLK(1) Quad DDR 1Fh 3 Figure 83
SRC-INT-QD INTCLK(3) Quad DDR 5Fh 3 Figure 84
SRC-IB2-QD INTCLK / 2(3) Quad DDR 9Fh 3
SRC-IB4-QD INTCLK / 4(3) Quad DDR DFh 3
(1) The EXTCLK option is not recommended when operating with DVDD< 2.35 V.
(2) Any of the four values can be used; see the Protocols for Configuring the Device section for more information.
(3) The device supports INTCLK, INTCLK / 2, and INTCLK / 4 options only for data transfer operations in zone 1. The EXTCLK option is supported in zone 1 and zone 2; see Figure 44.

Figure 73 to Figure 84 show the details of various source synchronous protocols. Table 9 shows the number of output clocks required in an optimal read frame for the different output protocol selections.

ADS8910B ADS8912B ADS8914B SRC-EC-1-SDR_bas707.gifFigure 73. SRC-EXT-SS: SRC, SCLK, Single SDO, SDR
ADS8910B ADS8912B ADS8914B SRC-EC-1-DDR_bas707.gifFigure 75. SRC-EXT-SD: SRC, SCLK, Single SDO, DDR
ADS8910B ADS8912B ADS8914B SRC-EC-2-SDR_bas707.gifFigure 77. SRC-EXT-DS: SRC, SCLK, Dual SDO, SDR
ADS8910B ADS8912B ADS8914B SRC-IC-1-SDR_bas707.gifFigure 74. SRC-INT-SS: SRC, INTCLK, Single SDO, SDR
ADS8910B ADS8912B ADS8914B SRC-IC-1-DDR_bas707.gifFigure 76. SRC-INT-SD: SRC, INTCLK, Single SDO, DDR
ADS8910B ADS8912B ADS8914B SRC-IC-2-SDR_bas707.gifFigure 78. SRC-INT-DS: SRC, INTCLK, Dual SDO, SDR
ADS8910B ADS8912B ADS8914B SRC-EC-2-DDR_bas707.gifFigure 79. SRC-EXT-DD: SRC, SCLK, Dual SDO, DDR
ADS8910B ADS8912B ADS8914B SRC-EC-4-SDR_bas707.gifFigure 81. SRC-EXT-QS: SRC, SCLK, Quad SDO, SDR
ADS8910B ADS8912B ADS8914B SRC-EC-4-DDR_bas707.gifFigure 83. SRC-EXT-QD: SRC, SCLK, Quad SDO, DDR
ADS8910B ADS8912B ADS8914B SRC-IC-2-DDR_bas707.gifFigure 80. SRC-INT-DD: SRC, INTCLK, Dual SDO, DDR
ADS8910B ADS8912B ADS8914B SRC-IC-4-SDR_bas707.gifFigure 82. SRC-INT-QS: SRC, INTCLK, Quad SDO, SDR
ADS8910B ADS8912B ADS8914B SRC-IC-4-DDR_bas707.gifFigure 84. SRC-INT-QD: SRC, INTCLK, Quad SDO, DDR