JAJSFT4C August   2018  – June 2019 ADS9224R , ADS9234R

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS92x4R
    6. 6.6  Electrical Characteristics: ADS9224R
    7. 6.7  Electrical Characteristics: ADS9234R
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics: ADS9224R
    11. 6.11 Typical Characteristics: ADS9234R
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Modules
        1. 7.3.1.1 Analog Input With Sample-and-Hold
        2. 7.3.1.2 ADC Transfer Function
      2. 7.3.2 Internal Reference Voltage
      3. 7.3.3 Reference Buffers
      4. 7.3.4 REFby2 Buffer
      5. 7.3.5 Data Averaging
        1. 7.3.5.1 Averaging of Two Samples
        2. 7.3.5.2 Averaging of Four Samples
    4. 7.4 Device Functional Modes
      1. 7.4.1 ACQ State
      2. 7.4.2 CNV State
      3. 7.4.3 Reset or Power-Down
        1. 7.4.3.1 Reset
        2. 7.4.3.2 Power-Down
      4. 7.4.4 Conversion Control and Data Transfer Frame
        1. 7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)
        2. 7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)
    5. 7.5 READY/STROBE Output
      1. 7.5.1 READY Output
      2. 7.5.2 STROBE Output
    6. 7.6 Programming
      1. 7.6.1 Output Data Word
      2. 7.6.2 Data Transfer Protocols
        1. 7.6.2.1 Protocols for Reading From the Device
          1. 7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)
          2. 7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
          3. 7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR)
          4. 7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)
          5. 7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)
        2. 7.6.2.2 Device Setup
          1. 7.6.2.2.1 Single Device: All Enhanced-SPI Options
          2. 7.6.2.2.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.6.2.3 Protocols for Configuring the Device
      3. 7.6.3 Reading and Writing Registers
    7. 7.7 Register Maps
      1. 7.7.1 ADS92x4R Registers
        1. 7.7.1.1 DEVICE_STATUS Register (Offset = 0h) [reset = 0h]
          1. Table 12. DEVICE_STATUS Register Field Descriptions
        2. 7.7.1.2 POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]
          1. Table 13. POWER_DOWN_CFG Register Field Descriptions
        3. 7.7.1.3 PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]
          1. Table 14. PROTOCOL_CFG Register Field Descriptions
        4. 7.7.1.4 BUS_WIDTH Register (Offset = 3h) [reset = 0h]
          1. Table 15. BUS_WIDTH Register Field Descriptions
        5. 7.7.1.5 CRT_CFG Register (Offset = 4h) [reset = 0h]
          1. Table 16. CRT_CFG Register Field Descriptions
        6. 7.7.1.6 OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]
          1. Table 17. OUTPUT_DATA_WORD_CFG Register Field Descriptions
        7. 7.7.1.7 DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]
          1. Table 18. DATA_AVG_CFG Register Field Descriptions
        8. 7.7.1.8 REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]
          1. Table 19. REFBY2_OFFSET Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
        1. 8.1.1.1 Charge-Kickback Filter
      2. 8.1.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics: ADS92x4R

at AVDD = 4.5 V to 5.5V, DVDD = 2.35 V to 5.5 V, VCM = VREFP_x/2, Internal reference and maximum throughput (unless otherwise noted); minimum and maximum values at TA = -40℃ to +125℃; typical values at TA = 25℃, AVDD = 5V, DVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUT
FSR(2) Full-scale input voltage (AINP_x - AINM_x) -4.096 4.096 V
VIN Absolute input voltage (AINP_x or AINM_x to GND) 0 4.096 V
VCM Common-mode input range 1.848 2.248 V
IIN Analog input leakage current ±1 µA
Ci Input capacitance Sample mode 16 pF
Hold mode 1
BW Analog input bandwidth -3-dB input signal 52 MHz
-0.1-dB input signal 4.2 MHz
VOLTAGE REFERENCE OUTPUT
VREFOUT(1)  REFOUT voltage 2.496 2.5 2.504 V
ΔVREF/ΔT VREFOUT drift 5.5 15 ppm/°C
ΔVREFOUT/ΔAVDD VREFOUT line regulation AVDD variation 4.5 V to 5.5 V 200 µV/V
IREFOUT REFOUT output current capability |ΔVREF| < 2 mV 1.5 µA
CREFOUT REFOUT capacitor For specified performance 1 µF
INTERNAL REFERENCE BUFFER
GREFBUF Reference buffer Gain 1.6388 V/V
EO-REFBUF Reference buffer output offset –1 ±0.2 1 mV
ΔEO-REFBUF/ΔT Reference buffer output offset temperature drift 10 µV/℃
(VREFP_A - VREFP_B) Reference buffer output mismatch –500 ±50 500 µV
CREFP_x Reference buffer output capacitor For specified performance, between each pair of REFP_x and REFM_x 7 10 27 µF
REFby2 OUTPUT
VREFby2 REFby2 output voltage EN_REFBY2_OFFSET = 0 2.043 2.048 2.053 V
EN_REFBY2_OFFSET = 1 2.133 2.148 2.163 V
IREFby2 REFby2 output current capability ±3 mA
REFby2 output capacitor 1 µF
REFby2 output noise With specified output capacitor 10 µVRMS
Digital Outputs
VOH High level output voltage IOH = 500-µA source 0.8 × DVDD DVDD V
VOL Low level output voltage IOL = 500-µA sink 0 0.2 × DVDD V
Digital Inputs
VIH High level input voltage DVDD > 2.3 V 0.7 × DVDD DVDD +0.3 V
VIL Low level intput voltage –0.3 0.3 × DVDD V
VIH High level input voltage DVDD ≤ 2.3 V 0.8 × DVDD DVDD +0.3 V
VIL Low level intput voltage –0.3 0.2 × DVDD V
Power Supply
AVDD Analog supply voltage 4.5 5 5.5 V
DVDD Digital supply voltage 1.65 3.3 5.5 V
IAVDD Analog supply current  fSAMPLE = 3 MSPS 24.3 30.4 mA
AVDD = 5 V, no conversion 7.8 mA
Power down (PD/RST Low) 1 µA
IDVDD Digital supply current  fSAMPLE = 3 MSPS, CSDO-x/y = 10 pF 2.8 mA
PSRR(1) Power-supply rejection ratio 100-mVPP Ripple on AVDD of frequency < 100kHz 70 dB
(1) Does not include the variation in voltage resulting from solder shift effects.
(2) Ideal input span; does not include gain or offset error.