JAJSFT4C August 2018 – June 2019 ADS9224R , ADS9234R
PRODUCTION DATA.
To enter reset state, the host controller pulls and keeps the PD/RST pin low for a duration of tWL_RST (tWL_RST-min ≤ tWL_RST ≤ tWL_RST-max).
In reset state, the device terminates the ongoing conversion or acquisition process and all configuration registers (see the Register Maps section) are reset to their default values.
After a delay of tRST-WKUP, the device enters ACQ state.