JAJSFT4C August   2018  – June 2019 ADS9224R , ADS9234R

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS92x4R
    6. 6.6  Electrical Characteristics: ADS9224R
    7. 6.7  Electrical Characteristics: ADS9234R
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics: ADS9224R
    11. 6.11 Typical Characteristics: ADS9234R
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Modules
        1. 7.3.1.1 Analog Input With Sample-and-Hold
        2. 7.3.1.2 ADC Transfer Function
      2. 7.3.2 Internal Reference Voltage
      3. 7.3.3 Reference Buffers
      4. 7.3.4 REFby2 Buffer
      5. 7.3.5 Data Averaging
        1. 7.3.5.1 Averaging of Two Samples
        2. 7.3.5.2 Averaging of Four Samples
    4. 7.4 Device Functional Modes
      1. 7.4.1 ACQ State
      2. 7.4.2 CNV State
      3. 7.4.3 Reset or Power-Down
        1. 7.4.3.1 Reset
        2. 7.4.3.2 Power-Down
      4. 7.4.4 Conversion Control and Data Transfer Frame
        1. 7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)
        2. 7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)
    5. 7.5 READY/STROBE Output
      1. 7.5.1 READY Output
      2. 7.5.2 STROBE Output
    6. 7.6 Programming
      1. 7.6.1 Output Data Word
      2. 7.6.2 Data Transfer Protocols
        1. 7.6.2.1 Protocols for Reading From the Device
          1. 7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)
          2. 7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
          3. 7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR)
          4. 7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)
          5. 7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)
        2. 7.6.2.2 Device Setup
          1. 7.6.2.2.1 Single Device: All Enhanced-SPI Options
          2. 7.6.2.2.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.6.2.3 Protocols for Configuring the Device
      3. 7.6.3 Reading and Writing Registers
    7. 7.7 Register Maps
      1. 7.7.1 ADS92x4R Registers
        1. 7.7.1.1 DEVICE_STATUS Register (Offset = 0h) [reset = 0h]
          1. Table 12. DEVICE_STATUS Register Field Descriptions
        2. 7.7.1.2 POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]
          1. Table 13. POWER_DOWN_CFG Register Field Descriptions
        3. 7.7.1.3 PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]
          1. Table 14. PROTOCOL_CFG Register Field Descriptions
        4. 7.7.1.4 BUS_WIDTH Register (Offset = 3h) [reset = 0h]
          1. Table 15. BUS_WIDTH Register Field Descriptions
        5. 7.7.1.5 CRT_CFG Register (Offset = 4h) [reset = 0h]
          1. Table 16. CRT_CFG Register Field Descriptions
        6. 7.7.1.6 OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]
          1. Table 17. OUTPUT_DATA_WORD_CFG Register Field Descriptions
        7. 7.7.1.7 DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]
          1. Table 18. DATA_AVG_CFG Register Field Descriptions
        8. 7.7.1.8 REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]
          1. Table 19. REFBY2_OFFSET Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
        1. 8.1.1.1 Charge-Kickback Filter
      2. 8.1.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)

In clock re-timer (CRT) protocols, the device sends out data on the SDO lines with a synchronized clock on the STROBE line. The data are synchronized to the rising edges of the STROBE pulses. For CRT protocols with a single data rate, the host can capture data on the falling edges of the STROBE pulses. For double data rate, the host must capture data on both edges of STROBE. The clock source for the STROBE output can be selected as an external clock (SCLK) or an internal clock by configuring the CRT_CLK_SELECT bits in the CRT_CFG register. For reading data from the device, SCLK is only required when the STROBE output is selected as an external clock. The SDOs that are not enabled by the BUS_WIDTH register are set to tri-state. Table 6 provides the details of different CRT protocols to read data from the device.

Table 6. CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, and CRT-Q-DDR Protocols for Reading From Device

PROTOCOL(1) SCLK POLARITY(2) CAPTURE EDGE MSB LAUNCH EDGE BUS WIDTH(4) tREAD(3) TIMING DIAGRAM
CRT-S-SDR Low (CPOL = 0) STROBE falling 1st STROBE rising 1 [15.5 × tSTROBE + m] Figure 56
CRT-D-SDR Low (CPOL = 0) STROBE falling 1st STROBE rising 2 [7.5 × tSTROBE + m] Figure 58
CRT-Q-SDR Low (CPOL = 0) STROBE falling 1st STROBE rising 4 [3.5 × tSTROBE + m] Figure 60
CRT-S-DDR Low (CPOL = 0) STROBE rising and falling 1st STROBE rising 1 [7.5 × tSTROBE + m] Figure 57
CRT-D-DDR Low (CPOL = 0) STROBE rising and falling 1st STROBE rising 2 [3.5× tSTROBE + m] Figure 59
CRT-Q-DDR Low (CPOL = 0) STROBE rising and falling 1st STROBE rising 4 [1.5 × tSTROBE + m] Figure 61
(1) For CRT protocols with SDR, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 010b. For CRT protocols with DDR, set the SDO_PROTOCOL bits to 011b in the PROTOCOL_CFG register.
(2) The device only supports CPOL = 0 for CRT protocols with an external clock.
(3) tREAD is the read time for reading the 16-bit output data word. For an external clock m = (tSU_CSCK + tHT_CKCS), and for an internal clock m = tD_CS_STROBE.
(4) For configuring the bus width, configure the BUS_WIDTH register.

Figure 56 through Figure 61 illustrate timing diagrams for the CRT-S-SDR, CRT-S-DDR, CRT-D-SDR, CRT-D-DDR, CRT-Q-SDR, and CRT-Q-DDR protocols, respectively.

ADS9224R ADS9234R SRC-00-S-SDR-SBAS876.gifFigure 56. CRT-S-SDR Protocol
ADS9224R ADS9234R SRC-00-S-DDR-SBAS876.gifFigure 57. CRT-S-DDR Protocol
ADS9224R ADS9234R SRC-00-D-SDR-SBAS876.gifFigure 58. CRT-D-SDR Protocol
ADS9224R ADS9234R SRC-00-Q-SDR-SBAS876.gifFigure 60. CRT-Q-SDR Protocol
ADS9224R ADS9234R SRC-00-D-DDR-SBAS876.gifFigure 59. CRT-D-DDR Protocol
ADS9224R ADS9234R SRC-00-Q-DDR-SBAS876.gifFigure 61. CRT-Q-DDR Protocol

For reading data, SCLK is only required when the STROBE output is selected as SCLK (external clock) in the CRT_CFG register. However, for configuring registers, SCLK is always required.