JAJSFT4C August 2018 – June 2019 ADS9224R , ADS9234R
PRODUCTION DATA.
The device supports an SPI protocol for writing into the device with all combinations of clock polarity and phase. On power-up or after reset, the device supports the SPI-00-S protocol for configuring the device. of As shown in Table 8, the host controller can use any of the four legacy, SPI-compatible protocols (SPI-00-S, SPI- 01-S, SPI-10-S, or SPI-11-S) to write data to the device.
PROTOCOL | SCLK POLARITY (CPOL)(1) | SCLK PHASE (CPHA)(1) | MSB CAPTURE EDGE | tWRITE(2) | TIMING DIAGRAM |
---|---|---|---|---|---|
SPI-00-S | Low (CPOL= 0) | Rising (CPHA = 0) | 1st SCLK rising | [15.5 × tCLK + k] | Figure 68 |
SPI-01-S | Low (CPOL= 0) | Falling (CPHA = 1) | 1st SCLK falling | [15.5 × tCLK + k] | Figure 69 |
SPI-10-S | High (CPOL= 1) | Falling (CPHA = 1) | 1st SCLK falling | [15.5 × tCLK + k] | Figure 68 |
SPI-11-S | High (CPOL= 1) | Rising (CPHA = 0) | 1st SCLK rising | [15.5 × tCLK + k] | Figure 69 |
Figure 68 and Figure 69 show timing diagrams for the SPI-00-S, SPI-10-S and SPI-01-S, SPI-11-S protocols, respectively, for configuring the device.