JAJSFT4C August   2018  – June 2019 ADS9224R , ADS9234R

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      代表的なアプリケーションの図
  4. 4 改訂履歴
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: ADS92x4R
    6. 6.6  Electrical Characteristics: ADS9224R
    7. 6.7  Electrical Characteristics: ADS9234R
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics: ADS9224R
    11. 6.11 Typical Characteristics: ADS9234R
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Converter Modules
        1. 7.3.1.1 Analog Input With Sample-and-Hold
        2. 7.3.1.2 ADC Transfer Function
      2. 7.3.2 Internal Reference Voltage
      3. 7.3.3 Reference Buffers
      4. 7.3.4 REFby2 Buffer
      5. 7.3.5 Data Averaging
        1. 7.3.5.1 Averaging of Two Samples
        2. 7.3.5.2 Averaging of Four Samples
    4. 7.4 Device Functional Modes
      1. 7.4.1 ACQ State
      2. 7.4.2 CNV State
      3. 7.4.3 Reset or Power-Down
        1. 7.4.3.1 Reset
        2. 7.4.3.2 Power-Down
      4. 7.4.4 Conversion Control and Data Transfer Frame
        1. 7.4.4.1 Conversion Control and Data Transfer Frame With Zero Cycle Latency (Zone 1 Transfer)
        2. 7.4.4.2 Conversion Control and Data Transfer Frame With Wide Read Cycle (Zone 2 Transfer)
    5. 7.5 READY/STROBE Output
      1. 7.5.1 READY Output
      2. 7.5.2 STROBE Output
    6. 7.6 Programming
      1. 7.6.1 Output Data Word
      2. 7.6.2 Data Transfer Protocols
        1. 7.6.2.1 Protocols for Reading From the Device
          1. 7.6.2.1.1 Legacy, SPI-Compatible Protocols (SPI-xy-S-SDR)
          2. 7.6.2.1.2 SPI-Compatible Protocols With Bus Width Options and Single Data Rate (SPI-xy-D-SDR and SPI-xy-Q-SDR)
          3. 7.6.2.1.3 SPI-Compatible Protocols With Bus Width Options and Double Data Rate (SPI-x1-S-DDR, SPI-x1-D-DDR, SPI-x1-Q-DDR)
          4. 7.6.2.1.4 Clock Re-Timer (CRT) Protocols (CRT-S-SDR, CRT-D-SDR, CRT-Q-SDR, CRT-S-DDR, CRT-D-DDR, CRT-Q-DDR)
          5. 7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)
        2. 7.6.2.2 Device Setup
          1. 7.6.2.2.1 Single Device: All Enhanced-SPI Options
          2. 7.6.2.2.2 Single Device: Minimum Pins for a Standard SPI Interface
        3. 7.6.2.3 Protocols for Configuring the Device
      3. 7.6.3 Reading and Writing Registers
    7. 7.7 Register Maps
      1. 7.7.1 ADS92x4R Registers
        1. 7.7.1.1 DEVICE_STATUS Register (Offset = 0h) [reset = 0h]
          1. Table 12. DEVICE_STATUS Register Field Descriptions
        2. 7.7.1.2 POWER_DOWN_CFG Register (Offset = 1h) [reset = 0h]
          1. Table 13. POWER_DOWN_CFG Register Field Descriptions
        3. 7.7.1.3 PROTOCOL_CFG Register (Offset = 2h) [reset = 0h]
          1. Table 14. PROTOCOL_CFG Register Field Descriptions
        4. 7.7.1.4 BUS_WIDTH Register (Offset = 3h) [reset = 0h]
          1. Table 15. BUS_WIDTH Register Field Descriptions
        5. 7.7.1.5 CRT_CFG Register (Offset = 4h) [reset = 0h]
          1. Table 16. CRT_CFG Register Field Descriptions
        6. 7.7.1.6 OUTPUT_DATA_WORD_CFG Register (Offset = 5h) [reset = 0h]
          1. Table 17. OUTPUT_DATA_WORD_CFG Register Field Descriptions
        7. 7.7.1.7 DATA_AVG_CFG Register (Offset = 6h) [reset = 0h]
          1. Table 18. DATA_AVG_CFG Register Field Descriptions
        8. 7.7.1.8 REFBY2_OFFSET Register (Offset = 7h) [reset = 0h]
          1. Table 19. REFBY2_OFFSET Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 ADC Input Driver
        1. 8.1.1.1 Charge-Kickback Filter
      2. 8.1.2 Input Amplifier Selection
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Signal Path
      2. 10.1.2 Grounding and PCB Stack-Up
      3. 10.1.3 Decoupling of Power Supplies
      4. 10.1.4 Reference Decoupling
      5. 10.1.5 Differential Input Decoupling
    2. 10.2 Layout Example
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 開発サポート
    2. 11.2 関連資料
    3. 11.3 関連リンク
    4. 11.4 ドキュメントの更新通知を受け取る方法
    5. 11.5 コミュニティ・リソース
    6. 11.6 商標
    7. 11.7 静電気放電に関する注意事項
    8. 11.8 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6.2.1.5 Parallel Byte Protocols (PB-xy-AB-SDR, PB-xy-AA-SDR)

In parallel byte protocols, the device sends out data from each ADC on all SDO lines in a byte format. The device supports all combinations of CPOL and CPHA in these protocols. The format of the data byte for these protocols can be set by the PARALLEL_MODE_DATA_FORMAT bits in the OUTPUT_DATA_WORD_CFG register. The device only supports a single data rate (SDR) in parallel byte protocols. Table 7 provides the details of different parallel byte protocols to read data from the device.

Table 7. PB-xy-AB-SDR, PB-xy-AA-SDR Protocols for Reading Data

PROTOCOL(1) SCLK POLARITY (CPOL)(2) SCLK PHASE (CPHA) MSB LAUNCH EDGE DATA FORMAT(4) tREAD(3) TIMING DIAGRAM
PB-00-AB-SDR Low (CPOL = 0) Rising (CPHA = 0) CS falling AB [3.5 × tCLK + k] Figure 62
PB-01-AB-SDR Low (CPOL = 0) Falling (CPHA = 1) 1st SCLK rising AB [3.5 × tCLK + k] Figure 63
PB-10-AB-SDR High (CPOL = 1) Falling (CPHA = 1) CS falling AB [3.5 × tCLK + k] Figure 62
PB-11-AB-SDR High (CPOL = 1) Rising (CPHA = 0) 1st SCLK falling AB [3.5 × tCLK + k] Figure 63
PB-00-AA-SDR Low (CPOL = 0) Rising (CPHA = 0) CS falling AA [3.5 × tCLK + k] Figure 64
PB-01-AA-SDR Low (CPOL = 0) Falling (CPHA = 1) 1st SCLK rising AA [3.5 × tCLK + k] Figure 65
PB-10-AA-SDR High (CPOL = 1) Falling (CPHA = 1) CS falling AA [3.5 × tCLK + k] Figure 64
PB-11-AA-SDR High (CPOL = 1) Rising (CPHA = 0) 1st SCLK falling AA [3.5 × tCLK + k] Figure 65
(1) For parallel byte protocols, set the SDO_PROTOCOL bits in the PROTOCOL_CFG register to 1xxb.
(2) Configure the SPI_CPOL and SPI_CPHA bits in the PROTOCOL_CFG register for the desired CPOL and CPHA.
(3) tREAD is the read time for reading the 16-bit output data word. k = (tSU_CSCK + tHT_CKCS).
(4) For selecting the data format for parallel byte protocols, configure the PARALLEL_MODE_DATA_FORMAT bits in the OUTPUT_DATA_WORD_CFG register.

Figure 62, Figure 63, Figure 64, and Figure 65 illustrate timing diagrams for the PB-00-AB-SDR and PB-10-AB-SDR, protocols, PB-01-AB-SDR and PB-11-AB-SDR, PB-00-AA-SDR and PB-10-AA-SDR, and PB-01-AA-SDR and PB-11-AA-SDR, respectively.

ADS9224R ADS9234R PB-x0-AB-SDR-SBAS876.gifFigure 62. PB-00-AB-SDR and PB-10-AB-SDR Protocols
ADS9224R ADS9234R PB-x0-AA-SDR-SBAS876.gifFigure 64. PB-00-AA-SDR and PB-10-AA-SDR Protocols
ADS9224R ADS9234R PB-x1-AB-SDR-SBAS876.gifFigure 63. PB-01-AB-SDR and PB-11-AB-SDR Protocols
ADS9224R ADS9234R PB-x1-AA-SDR-SBAS876.gifFigure 65. PB-01-AA-SDR and PB-11-AA-SDR Protocols