JAJSHL6E August   2010  – June 2019 AFE031

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Thermal Information
    4. 8.4  Electrical Characteristics: Transmitter (Tx)
    5. 8.5  Electrical Characteristics: Power Amplifier (PA)
    6. 8.6  Electrical Characteristics: Receiver (Rx)
    7. 8.7  Electrical Characteristics: Digital
    8. 8.8  Electrical Characteristics: Two-Wire Interface
    9. 8.9  Electrical Characteristics: Internal Bias Generator
    10. 8.10 Electrical Characteristics: Power Supply
    11. 8.11 Timing Requirements
    12. 8.12 Timing Diagrams
    13. 8.13 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 PA Block
      2. 9.2.2 Tx Block
      3. 9.2.3 Rx Block
      4. 9.2.4 DAC Block
      5. 9.2.5 REF1 and REF2 Blocks
      6. 9.2.6 Zero Crossing Detector Block
      7. 9.2.7 ETx and ERx Blocks
    3. 9.3 Power Supplies
    4. 9.4 Pin Descriptions
      1. 9.4.1 Current Overload
      2. 9.4.2 Thermal Overload
    5. 9.5 Calibration Modes
      1. 9.5.1 Tx Calibration Mode
      2. 9.5.2 Rx Calibration Mode
    6. 9.6 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Design Procedure
        1. 10.2.1.1 Line-Coupling Circuit
        2. 10.2.1.2 Circuit Protection
        3. 10.2.1.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 電力線通信開発者用キット
        2. 11.1.2.2 TINA-TI™ (無料のダウンロード・ソフトウェア)
        3. 11.1.2.3 TI Precision Designs
        4. 11.1.2.4 WEBENCH Filter Designer
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

9.3 Power Supplies

The AFE031 has two low-voltage analog power-supply pins and one low-voltage digital supply pin. Internally, the two analog supply pins are connected to each other through back-to-back electrostatic discharge (ESD) protection diodes. These pins must be connected to each other on the application printed circuit board (PCB). It is also recommended to connect the digital supply pin and the two analog supply pins together on the PCB. Both low-voltage analog ground pins are also connected internally through back-to-back ESD protection diodes. These ground pins should also be connected to the digital ground pin on the PCB. It is recommended to bypass the low-voltage power supplies with a parallel combination of a 10-μf and 100-nf capacitor. The PA block is biased separately from a high-voltage, high-current supply.

Two PA power supply pins and two PA ground pins are available to provide a path for the high currents associated with driving the low impedance of the ac mains. Connecting the two PA supply pins together is recommended. It is also recommended to place a bypass capacitor of 47 μF to 100 μF in parellel with 100 nF as close as possible to the AFE031. Care must be taken when routing the high current ground lines on the PCB to avoid creating voltage drops in the PCB ground that may vary with changes in load current.

The AFE031 has many options to enable or disable the functional blocks to allow for flexible power-savings modes. Table 7 shows the specific power supply that each functional block draws power from, as well as the typical amount of power drawn from the associated power supplies for both the enabled and disabled states. For additional information on power-supply requirements refer to Application Report SBOA130, Analog Front-End Design for a Narrowband Power-Line Communications Modem Using the AFE031 (available for download at www.ti.com).

Table 7. Power Consumption with Enable and Disable Times (Typical)

BLOCK STATUS ENABLE TIME DISABLE TIME AVDD SUPPLY CURRENT DVDD SUPPLY CURRENT PA SUPPLY CURRENT
PA On 10 μs – – – 61 mA
Off – 10 μs – – 70 μA
Tx On 10 μs – 3.7 mA – –
Off – 10 μs 1 μA – –
Rx On 10 μs – 5.3 mA – –
Off – 10 μs 1 μA – –
ERx On 10 μs – 900 μA – –
Off – 10 μs 1 μA – –
ETx On 10 μs – 1.2 mA – –
Off – 10 μs 1 μA – –
DAC On 10 μs – – 16 μA –
Off – 10 μs – 1 μA –
ZC On 10 μs – 25 μA – –
Off – 10 μs 1 μA – –
REF1 On 10 μs – – – 26 μA
Off – 10 μs – – 8 μA
REF2 On 10 μs – 25 μA – –
Off – 10 μs 4 μA – –