JAJSHL6E August   2010  – June 2019 AFE031

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
  4. 4 改訂履歴
  5. 5 概要 (続き)
  6. 6 Device Comparison Table
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Thermal Information
    4. 8.4  Electrical Characteristics: Transmitter (Tx)
    5. 8.5  Electrical Characteristics: Power Amplifier (PA)
    6. 8.6  Electrical Characteristics: Receiver (Rx)
    7. 8.7  Electrical Characteristics: Digital
    8. 8.8  Electrical Characteristics: Two-Wire Interface
    9. 8.9  Electrical Characteristics: Internal Bias Generator
    10. 8.10 Electrical Characteristics: Power Supply
    11. 8.11 Timing Requirements
    12. 8.12 Timing Diagrams
    13. 8.13 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Functional Block Diagram
    2. 9.2 Feature Description
      1. 9.2.1 PA Block
      2. 9.2.2 Tx Block
      3. 9.2.3 Rx Block
      4. 9.2.4 DAC Block
      5. 9.2.5 REF1 and REF2 Blocks
      6. 9.2.6 Zero Crossing Detector Block
      7. 9.2.7 ETx and ERx Blocks
    3. 9.3 Power Supplies
    4. 9.4 Pin Descriptions
      1. 9.4.1 Current Overload
      2. 9.4.2 Thermal Overload
    5. 9.5 Calibration Modes
      1. 9.5.1 Tx Calibration Mode
      2. 9.5.2 Rx Calibration Mode
    6. 9.6 Serial Interface
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Detailed Design Procedure
        1. 10.2.1.1 Line-Coupling Circuit
        2. 10.2.1.2 Circuit Protection
        3. 10.2.1.3 Thermal Considerations
  11. 11デバイスおよびドキュメントのサポート
    1. 11.1 デバイス・サポート
      1. 11.1.1 デベロッパー・ネットワークの製品に関する免責事項
      2. 11.1.2 開発サポート
        1. 11.1.2.1 電力線通信開発者用キット
        2. 11.1.2.2 TINA-TI™ (無料のダウンロード・ソフトウェア)
        3. 11.1.2.3 TI Precision Designs
        4. 11.1.2.4 WEBENCH Filter Designer
    2. 11.2 ドキュメントのサポート
      1. 11.2.1 関連資料
    3. 11.3 ドキュメントの更新通知を受け取る方法
    4. 11.4 コミュニティ・リソース
    5. 11.5 商標
    6. 11.6 静電気放電に関する注意事項
    7. 11.7 Glossary
  12. 12メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

10.1 Application Information

The AFE031 is an integrated powerline communication analog front-end (AFE) device built from a variety of functional blocks that work in conjunction with a microcontroller. The AFE031 provides the interface between the microcontroller and a line coupling circuit. The AFE031 delivers high performance and is designed to work with a minimum number of external components. Consisting of a variety of functional and configurable blocks, the AFE031 simplifies design efforts and reduces the time to market of many applications.

The AFE031 includes three primary functional blocks:

  • Power Amplifier (PA)
  • Transmitter (Tx)
  • Receiver (Rx)

The AFE031 also consists of other support circuitry blocks that provide zero crossing detection, an additional two-wire communications channel, and power-saving biasing blocks (see the ). All of these functional blocks are digitally controlled by the microcontroller through the serial interface (SPI).

Figure 47 shows a typical powerline communications application system diagram. Table 19 is a complete list of the sections within the AFE031.

AFE031 ai_sys_bd_bos531.gifFigure 47. Typical Powerline Communications System Diagram

Table 19. Block Descriptions

BLOCK DESCRIPTION
PA The PA block includes the power amplifier and associated pedestal biasing circuitry
Tx The Tx block includes the Tx_Filter and the Tx_PGA
Rx The Rx block includes the Rx PGA1, the Rx Filter, and the Rx PGA2
ERx The ER block includes the two-wire receiver
ETx The ER block includes the two-wire transmitter
DAC The DAC block includes a digital-to-analog converter
ZC The ZC block includes both zero crossing detectors
REF1 The REF1 block includes the internal bias generator for the PA block
REF2 The REF2 block includes the internal bias generators for the Tx, Rx, ERx, and ETx blocks