AFEx32A3W support integrated ADC on channel 1. Connect
FB1 to VDD using a pullup resistor. Channel 1 must be configured as
a comparator. The transfer function of the ADC is given in Equation 4.
Equation 4.
where
- ADC_DATA is the
output of the ADC-DATA register.
- VIN is
the input voltage at the VOUT1/AIN1 pin.
- VFS is
the full-scale input voltage as provided in Table 6-3.
- N is the number
of ADC bits, 10.
- (INTEGER) denotes
integer division.
Table 6-3 Full Scale
Analog Input (VFS)
REFERENCE (VREF) |
GAIN |
VFS |
Power supply |
1 × |
VDD/3 |
Internal |
1.5 × |
(VREF × GAIN)/3 |
2 × |
(VREF × GAIN)/3 |
3 × |
(VREF × GAIN)/6 |
4 × |
(VREF × GAIN)/6 |
Follow these steps to
configure and read data from ADC on channel 1:
- Configure
the gain using the REF-GAIN-1 bits in the
DAC-1-GAIN-CMP-CONFIG register.
- Configure
DAC channel 1 as comparator by writing 1 to the
CMP-1-EN bit in the DAC-1-GAIN-CMP-CONFIG
register.
- Enable
the ADC (ADC-EN bit) and select the number of
averages (ADC-AVG) in the ADC-CONFIG-TRIG
register.
- Start the
ADC conversion by writing 1 to the TRIG-ADC bit in
the ADC-CONFIG-TRIG register.
- Read the
ADC data using the ADC-DATA register. The data is
valid when the ADC-DRDY bit is 1. Repeat steps 4 and
5 for every ADC readback.
Figure 6-8 shows the interface example for the ADC on channel 1.