JAJSLP3 june   2023 AFE43902-Q1 , AFE53902-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: ADC Input
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Requirements: PWM Output
    15. 6.15 Timing Diagrams
    16. 6.16 Typical Characteristics: Voltage Output
    17. 6.17 Typical Characteristics: ADC
    18. 6.18 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital-to-Analog Converter (DAC) Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Analog-to-Digital Converter (ADC) Mode
      4. 7.4.4 Multislope Thermal Foldback Mode
        1. 7.4.4.1 Thermistor Linearization
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 2068h]
      7. 7.6.7  DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      8. 7.6.8  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      9. 7.6.9  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      12. 7.6.12 Xx-TEMPERATURE Register (SRAM address = 20h, 22h, 24h) [reset = 0000h]
      13. 7.6.13 Yx-TEMPERATURE Register (SRAM address = 21h, 23h, 25h) [reset = 0000h]
      14. 7.6.14 Xx-OUTPUT Register (SRAM address = 26h, 28h, 2Ah, 2Ch) [reset = 0000h]
      15. 7.6.15 Yx-OUTPUT Register (SRAM address = 27h, 29h, 2Bh, 2Dh) [reset = 0000h]
      16. 7.6.16 PWM-FREQUENCY Register (SRAM address = 2Eh) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Multislope Thermal Foldback Using the AFE53902-Q1 and Voltage Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Multislope Thermal Foldback Using the AFE43902-Q1 and PWM Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Register Maps

Table 7-12 Register Map
REGISTER MOST SIGNIFICANT DATA BYTE (MSDB) LEAST SIGNIFICANT DATA BYTE (LSDB)
BIT15 BIT14 BIT13 BIT12 BIT11 BIT10 BIT9 BIT8 BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
NOP NOP
DAC-0-VOUT-CMP-CONFIG X VOUT-GAIN-0 X CMP-0-OD-EN CMP-0-OUT-EN CMP-0-HIZ-IN-DIS CMP-0-INV-EN CMP-0-EN
DAC-1-VOUT-CMP-CONFIG X VOUT-GAIN-1 X CMP-1-OD-EN CMP-1-OUT-EN CMP-1-HIZ-IN-DIS CMP-1-INV-EN CMP-1-EN
COMMON-CONFIG RESERVED DEV-LOCK RESERVED EN-INT-REF ADC-PDN-0 RESERVED VOUT-PDN-1 RESERVED
COMMON-TRIGGER DEV-UNLOCK RESET RESERVED NVM-PROG NVM-RELOAD
COMMON-PWM-TRIG RESERVED START-FUNCTION
GENERAL-STATUS NVM-CRC-FAIL-INT NVM-CRC-FAIL-USER X DAC-0-BUSY X DAC-1-BUSY NVM-BUSY DEVICE-ID
DEVICE-MODE-CONFIG RESERVED DIS-MODE-IN RESERVED SM-IO-EN RESERVED
INTERFACE-CONFIG X TIMEOUT-EN RESERVED FSDO-EN X SDO-EN
STATE-MACHINE-CONFIG0 RESERVED SM-ABORT SM-START SM-EN
SRAM-CONFIG X SRAM-ADDR
SRAM-DATA SRAM-DATA
X1-TEMPERATURE RESERVED X1-TEMPERATURE RESERVED
X2-TEMPERATURE RESERVED X2-TEMPERATURE RESERVED
X3-TEMPERATURE RESERVED X3-TEMPERATURE RESERVED
X4-TEMPERATURE RESERVED X4-TEMPERATURE RESERVED
Y1-TEMPERATURE RESERVED Y1-TEMPERATURE
Y2-TEMPERATURE RESERVED Y2-TEMPERATURE
Y3-TEMPERATURE RESERVED Y3-TEMPERATURE
Y4-TEMPERATURE RESERVED Y4-TEMPERATURE
X1-OUTPUT RESERVED X1-OUTPUT
X2-OUTPUT RESERVED X2-OUTPUT
X3-OUTPUT RESERVED X3-OUTPUT
X4-OUTPUT RESERVED X4-OUTPUT
Y1-OUTPUT RESERVED Y1-OUTPUT
Y2-OUTPUT RESERVED Y2-OUTPUT
Y3-OUTPUT RESERVED Y3-OUTPUT
Y4-OUTPUT RESERVED Y4-OUTPUT
PWM-FREQUENCY RESERVED PWM-FREQUENCY RESERVED
Note: Shaded cells indicate the register bits or fields that are stored in NVM.
Note: X = Don't care.
Table 7-13 Register Names
I2C/SPI ADDRESS SRAM ADDR REGISTER NAME SECTION
00h -- NOP Section 7.6.1
15h -- DAC-0-VOUT-CMP-CONFIG Section 7.6.2
03h -- DAC-1-VOUT-CMP-CONFIG Section 7.6.2
1Fh -- COMMON-CONFIG Section 7.6.3
20h -- COMMON-TRIGGER Section 7.6.4
21h -- COMMON-PWM-TRIG Section 7.6.5
22h -- GENERAL-STATUS Section 7.6.6
25h -- DEVICE-MODE-CONFIG Section 7.6.7
26h -- INTERFACE-CONFIG Section 7.6.8
27h -- STATE-MACHINE-CONFIG0 Section 7.6.9
2Bh -- SRAM-CONFIG Section 7.6.10
2Ch -- SRAM-DATA Section 7.6.11
-- 20h X1-TEMPERATURE Section 7.6.12
-- 21h Y1-TEMPERATURE Section 7.6.13
-- 22h X2-TEMPERATURE Section 7.6.12
-- 23h Y2-TEMPERATURE Section 7.6.13
-- 24h X3-TEMPERATURE Section 7.6.12
-- 25h Y3-TEMPERATURE Section 7.6.13
-- 26h X1-OUTPUT Section 7.6.14
-- 27h Y1-OUTPUT Section 7.6.15
-- 28h X2-OUTPUT Section 7.6.14
-- 29h Y2-OUTPUT Section 7.6.15
-- 2Ah X3-OUTPUT Section 7.6.14
-- 2Bh Y3-OUTPUT Section 7.6.15
-- 2Ch X4-OUTPUT Section 7.6.14
-- 2Dh Y4-OUTPUT Section 7.6.15
-- 2Eh PWM-FREQUENCY Section 7.6.16