JAJSLP3 june   2023 AFE43902-Q1 , AFE53902-Q1

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: Voltage Output
    6. 6.6  Electrical Characteristics: ADC Input
    7. 6.7  Electrical Characteristics: General
    8. 6.8  Timing Requirements: I2C Standard Mode
    9. 6.9  Timing Requirements: I2C Fast Mode
    10. 6.10 Timing Requirements: I2C Fast Mode Plus
    11. 6.11 Timing Requirements: SPI Write Operation
    12. 6.12 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
    13. 6.13 Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
    14. 6.14 Timing Requirements: PWM Output
    15. 6.15 Timing Diagrams
    16. 6.16 Typical Characteristics: Voltage Output
    17. 6.17 Typical Characteristics: ADC
    18. 6.18 Typical Characteristics: General
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Smart Analog Front End (AFE) Architecture
      2. 7.3.2 Programming Interface
      3. 7.3.3 Nonvolatile Memory (NVM)
        1. 7.3.3.1 NVM Cyclic Redundancy Check (CRC)
          1. 7.3.3.1.1 NVM-CRC-FAIL-USER Bit
          2. 7.3.3.1.2 NVM-CRC-FAIL-INT Bit
      4. 7.3.4 Power-On Reset (POR)
      5. 7.3.5 External Reset
      6. 7.3.6 Register-Map Lock
    4. 7.4 Device Functional Modes
      1. 7.4.1 Digital-to-Analog Converter (DAC) Mode
        1. 7.4.1.1 Voltage Reference and DAC Transfer Function
          1. 7.4.1.1.1 Power-Supply as Reference
          2. 7.4.1.1.2 Internal Reference
          3. 7.4.1.1.3 External Reference
      2. 7.4.2 Pulse-Width Modulation (PWM) Mode
      3. 7.4.3 Analog-to-Digital Converter (ADC) Mode
      4. 7.4.4 Multislope Thermal Foldback Mode
        1. 7.4.4.1 Thermistor Linearization
    5. 7.5 Programming
      1. 7.5.1 SPI Programming Mode
      2. 7.5.2 I2C Programming Mode
        1. 7.5.2.1 F/S Mode Protocol
        2. 7.5.2.2 I2C Update Sequence
          1. 7.5.2.2.1 Address Byte
          2. 7.5.2.2.2 Command Byte
        3. 7.5.2.3 I2C Read Sequence
    6. 7.6 Register Maps
      1. 7.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 7.6.2  DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
      3. 7.6.3  COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
      4. 7.6.4  COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
      5. 7.6.5  COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
      6. 7.6.6  GENERAL-STATUS Register (address = 22h) [reset = 2068h]
      7. 7.6.7  DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
      8. 7.6.8  INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
      9. 7.6.9  STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
      10. 7.6.10 SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
      11. 7.6.11 SRAM-DATA Register (address = 2Ch) [reset = 0000h]
      12. 7.6.12 Xx-TEMPERATURE Register (SRAM address = 20h, 22h, 24h) [reset = 0000h]
      13. 7.6.13 Yx-TEMPERATURE Register (SRAM address = 21h, 23h, 25h) [reset = 0000h]
      14. 7.6.14 Xx-OUTPUT Register (SRAM address = 26h, 28h, 2Ah, 2Ch) [reset = 0000h]
      15. 7.6.15 Yx-OUTPUT Register (SRAM address = 27h, 29h, 2Bh, 2Dh) [reset = 0000h]
      16. 7.6.16 PWM-FREQUENCY Register (SRAM address = 2Eh) [reset = 0000h]
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Multislope Thermal Foldback Using the AFE53902-Q1 and Voltage Output
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
        3. 8.2.1.3 Application Performance Plots
      2. 8.2.2 Multislope Thermal Foldback Using the AFE43902-Q1 and PWM Output
        1. 8.2.2.1 Design Requirements
        2. 8.2.2.2 Detailed Design Procedure
        3. 8.2.2.3 Application Performance Plots
    3. 8.3 Power Supply Recommendations
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 ドキュメントの更新通知を受け取る方法
    2. 9.2 サポート・リソース
    3. 9.3 Trademarks
    4. 9.4 静電気放電に関する注意事項
    5. 9.5 用語集
  11. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.5 Electrical Characteristics: Voltage Output

minimum and maximum specifications at –40°C ≤  TA ≤ +125°C and typical specifications at TA = 25°C, 1.7 V ≤ VDD ≤ 5.5 V, DAC reference tied to VDD, gain = 1 ×, DAC output pin (OUT) loaded with resistive load (RL = 5 kΩ to AGND) and capacitive load (CL = 200 pF to AGND), and digital inputs at VDD or AGND (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
STATIC PERFORMANCE
Resolution AFE53902-Q1 10 Bits
AFE43902-Q1 8
INL Integral nonlinearity(1) AFE53902-Q1 –1.25 1.25 LSB
AFE43902-Q1 –1 1
DNL Differential nonlinearity(1) –1 1 LSB
Zero-code error(2) Code 0d into DAC, external reference, VDD = 5.5 V 6 12 mV
Code 0d into DAC, internal VREF, gain = 4 ×,
VDD = 5.5 V		 6 15
Zero-code error temperature coefficient(2) ±10 µV/°C
Offset error(2) 1.7 V ≤ VDD < 2.7 V, VFB pin shorted to VOUT, DAC code: 8d for 10-bit resolution, 2d for 8-bit resolution –0.75 0.3 0.75 %FSR
2.7 V ≤ VDD ≤ 5.5 V, VFB pin shorted to VOUT, DAC code: 8d for 10-bit resolution, 2d for 8-bit resolution –0.5 0.25 0.5
Offset-error temperature coefficient(2) VFB pin shorted to VOUT, DAC code: 8d for 10-bit resolution, 2d for 8-bit resolution ±0.0003 %FSR/°C
Gain error(2) Between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution –0.5 0.25 0.5 %FSR
Gain-error temperature coefficient(2) Between end-point codes: 8d to 1016d for 10-bit resolution, 2d to 254d for 8-bit resolution ±0.0008 %FSR/°C
Full-scale error(2) 1.7 V ≤ VDD < 2.7 V, DAC at full-scale –1 1 %FSR
2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale, 10-bit resolution –0.6 0.6
2.7 V ≤ VDD ≤ 5.5 V, DAC at full-scale, 8-bit resolution –0.65 0.65
Full-scale-error temperature coefficient(2) DAC at full-scale ±0.0008 %FSR/°C
OUTPUT
Output voltage Reference tied to VDD 0 VDD V
CL Capacitive load(3) RL = infinite, phase margin = 30° 200 pF
Phase margin = 30° 1000
Short-circuit current VDD = 1.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 15 mA
VDD = 2.7 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 50
VDD = 5.5 V, full-scale output shorted to AGND or
zero-scale output shorted to VDD		 60
Output-voltage headroom(3) To VDD, DAC output unloaded, internal reference = 1.21 V, VDD ≥ 1.21 V × gain + 0.2 V 0.2 V
To VDD and to AGND,
DAC output unloaded, external reference at VDD (gain = 1 ×), the VREF pin is not shorted to VDD		 0.8 %FSR
To VDD and to AGND, ILOAD = 10 mA at VDD = 5.5 V, ILOAD = 3 mA at VDD = 2.7 V, ILOAD = 1 mA at VDD =
1.8 V, external reference at VDD (gain = 1 ×), the VREF pin is not shorted to VDD		 10
VOUT dc output impedance DAC output enabled and DAC code = midscale, 
VDD = 5.5 V, external reference mode		 0.007 Ω
DAC output enabled and DAC code = 8d, 
VDD = 5.5 V, external reference mode		 0.25
DAC output enabled and DAC code = 1016d, 
VDD = 5.5 V, external reference mode		 0.25
ZO VFB dc output impedance(4) DAC output enabled, internal reference (gain = 1.5 × or 2 ×) or external reference at VDD (gain = 1 ×), the VREF pin is not shorted to VDD 400 500 600 kΩ
DAC output enabled, internal VREF, gain = 3 × or 4 × 325 400 485
Power supply rejection ratio (dc) Internal VREF, gain = 2 ×, DAC at midscale,
VDD = 5 V ±10%		 0.25 mV/V
DYNAMIC PERFORMANCE
tsett Output voltage settling time 1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V 20 µs
1/4 to 3/4 scale and 3/4 to 1/4 scale settling to 10%FSR, VDD = 5.5 V, internal VREF, gain = 4 × 25
Slew rate VDD = 5.5 V 0.3 V/µs
Power-on glitch magnitude At start-up, DAC output disabled 75 mV
At start-up, DAC output disabled, RL = 100 kΩ 200
Output-enable glitch magnitude DAC output disabled to enabled, DAC registers at zero scale, RL = 100 kΩ 250 mV
Vn Output noise voltage (peak to peak) f = 0.1 Hz to 10 Hz, DAC at midscale, VDD = 5.5 V 50 µVPP
Internal VREF, gain = 4 ×, f = 0.1 Hz to 10 Hz,
DAC at midscale, VDD = 5.5 V		 90
Output noise density f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.35 µV/√Hz
Internal VREF, gain = 4 ×, f = 1 kHz, DAC at midscale, VDD = 5.5 V 0.9
Power supply rejection ratio (ac)(4) Internal VREF, gain = 4 ×, 200-mV 50-Hz or 60-Hz sine wave superimposed on power supply voltage, DAC at midscale -68 dB
Code change glitch impulse ±1 LSB change around midscale (including feedthrough) 10 nV-s
Code change glitch impulse magnitude ±1 LSB change around midscale (including feedthrough) 15 mV
(1) Measured with DAC output unloaded. For external reference and internal reference VDD ≥ 1.21 × gain + 0.2 V, between end-point codes: 8d to 1016d for 10-bit resolution and 2d to 254d for 8-bit resolution.
(2) Measured with DAC output unloaded.
(3) Specified by design and characterization, not production tested.
(4) Specified with 200-mV headroom with respect to reference value when internal reference is used.