JAJSLP3
june 2023
AFE43902-Q1
,
AFE53902-Q1
PRODUCTION DATA
1
1
特長
2
アプリケーション
3
概要
4
Revision History
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics: Voltage Output
6.6
Electrical Characteristics: ADC Input
6.7
Electrical Characteristics: General
6.8
Timing Requirements: I2C Standard Mode
6.9
Timing Requirements: I2C Fast Mode
6.10
Timing Requirements: I2C Fast Mode Plus
6.11
Timing Requirements: SPI Write Operation
6.12
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 0)
6.13
Timing Requirements: SPI Read and Daisy Chain Operation (FSDO = 1)
6.14
Timing Requirements: PWM Output
6.15
Timing Diagrams
6.16
Typical Characteristics: Voltage Output
6.17
Typical Characteristics: ADC
6.18
Typical Characteristics: General
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Smart Analog Front End (AFE) Architecture
7.3.2
Programming Interface
7.3.3
Nonvolatile Memory (NVM)
7.3.3.1
NVM Cyclic Redundancy Check (CRC)
7.3.3.1.1
NVM-CRC-FAIL-USER Bit
7.3.3.1.2
NVM-CRC-FAIL-INT Bit
7.3.4
Power-On Reset (POR)
7.3.5
External Reset
7.3.6
Register-Map Lock
7.4
Device Functional Modes
7.4.1
Digital-to-Analog Converter (DAC) Mode
7.4.1.1
Voltage Reference and DAC Transfer Function
7.4.1.1.1
Power-Supply as Reference
7.4.1.1.2
Internal Reference
7.4.1.1.3
External Reference
7.4.2
Pulse-Width Modulation (PWM) Mode
7.4.3
Analog-to-Digital Converter (ADC) Mode
7.4.4
Multislope Thermal Foldback Mode
7.4.4.1
Thermistor Linearization
7.5
Programming
7.5.1
SPI Programming Mode
7.5.2
I2C Programming Mode
7.5.2.1
F/S Mode Protocol
7.5.2.2
I2C Update Sequence
7.5.2.2.1
Address Byte
7.5.2.2.2
Command Byte
7.5.2.3
I2C Read Sequence
7.6
Register Maps
7.6.1
NOP Register (address = 00h) [reset = 0000h]
7.6.2
DAC-x-VOUT-CMP-CONFIG Register (address = 15h, 03h) [reset = 0400h]
7.6.3
COMMON-CONFIG Register (address = 1Fh) [reset = 03F9h]
7.6.4
COMMON-TRIGGER Register (address = 20h) [reset = 0000h]
7.6.5
COMMON-PWM-TRIG Register (address = 21h) [reset = 0001h]
7.6.6
GENERAL-STATUS Register (address = 22h) [reset = 2068h]
7.6.7
DEVICE-MODE-CONFIG Register (address = 25h) [reset = 8040h]
7.6.8
INTERFACE-CONFIG Register (address = 26h) [reset = 0000h]
7.6.9
STATE-MACHINE-CONFIG0 Register (address = 27h) [reset = 0003h]
7.6.10
SRAM-CONFIG Register (address = 2Bh) [reset = 0000h]
7.6.11
SRAM-DATA Register (address = 2Ch) [reset = 0000h]
7.6.12
Xx-TEMPERATURE Register (SRAM address = 20h, 22h, 24h) [reset = 0000h]
7.6.13
Yx-TEMPERATURE Register (SRAM address = 21h, 23h, 25h) [reset = 0000h]
7.6.14
Xx-OUTPUT Register (SRAM address = 26h, 28h, 2Ah, 2Ch) [reset = 0000h]
7.6.15
Yx-OUTPUT Register (SRAM address = 27h, 29h, 2Bh, 2Dh) [reset = 0000h]
7.6.16
PWM-FREQUENCY Register (SRAM address = 2Eh) [reset = 0000h]
8
Application and Implementation
8.1
Application Information
8.2
Typical Applications
8.2.1
Multislope Thermal Foldback Using the AFE53902-Q1 and Voltage Output
8.2.1.1
Design Requirements
8.2.1.2
Detailed Design Procedure
8.2.1.3
Application Performance Plots
8.2.2
Multislope Thermal Foldback Using the AFE43902-Q1 and PWM Output
8.2.2.1
Design Requirements
8.2.2.2
Detailed Design Procedure
8.2.2.3
Application Performance Plots
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
ドキュメントの更新通知を受け取る方法
9.2
サポート・リソース
9.3
Trademarks
9.4
静電気放電に関する注意事項
9.5
用語集
10
Mechanical, Packaging, and Orderable Information
パッケージ・オプション
メカニカル・データ(パッケージ|ピン)
RTE|16
MPQF149D
サーマルパッド・メカニカル・データ
RTE|16
QFND525B
発注情報
jajslp3_oa
7.3
Feature Description