JAJSVV8 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.5 Electrical Characteristics

Minimum and maximum values are across the full temperature range of TA = –40°C to TJ = +125°C, DRVDD = 3.3 V, AVDD3 = 3.3 V, AVDD18 = 1.8 V, DVDD18 = 1.8 V, –1-dBFS analog input ac-coupled with a 0.1-µF capacitor, AFE_CLK = 25 MHz, LNA gain = 15 dB, PGA gain = 0 dB, default mode, and differential input clock with 50% duty cycle, unless otherwise noted. Typical values are at TNOM = +25°C.
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
FULL-CHANNEL CHARACTERISTICS
Maximum differential input signal amplitude on INIP and INIMLNA gain = 12 dB0.5VPP
LNA gain = 15 dB (default)0.35
LNA gain = 16.5 dB0.3
LNA gain = 18 dB0.25
Input resistance, from each input to internal dc bias levelDefault1 ± 20%kΩ
TERM_INT_20K_LNA / TERM_INT_20K_AUX = 110 ± 20%
CIInput capacitanceDifferential input capacitance5.5pF
VVCMVCM output voltageVoltage on VCM pins1.45V
VCM output current capabilityFor 50-mV drop in VCM voltage3mA
Gain matchingAcross channels and devices0.151dB
EGGain errorPGA gain = 30 dB± 0.6± 1.4dB
EOOffset errorPGA gain = 30 dB, 1 sigma value± 120LSB
Input-referred noise voltagefIN = 3 MHz, idle channel, PGA gain = 30 dB (default)2.93.8nV/√ Hz
fIN = 3 MHz, idle channel, PGA gain = 30 dB
(HIGH_POW_LNA mode)		2.5
SNRSignal-to-noise ratiofIN = 3 MHz, main channel6567.7dBFS
fIN = 3 MHz, AUX channel69.2
SFDRSpurious-free dynamic rangefIN = 3 MHz, main channel (default)5766dBc
fIN = 3 MHz, main channel (HPL_EN mode)74
THDTotal harmonic distortionfIN = 3 MHz, main channel5665dBc
IMDIntermodulation distortionfIN1 = 1.5 MHz, fIN2 = 2 MHz, AIN1 and AIN2 = –7 dBFS83dBFS
PSRRPower-supply rejection ratioFor a 50-mVPP signal on AVDD18 up to 10 MHz, no input applied to analog inputs> 50dB
Number of bits in the ADC12Bits
Crosstalk, main channel to main channelAggressor channel: fIN = 2 MHz, 1 dB below ADC full-scale.
Victim channel: fIN= 3 MHz, 1 dB below ADC full-scale.		70dB
Maximum channel gainLNA gain = 18 dB, PGA gain = 30 dB48dB
Minimum channel gainLNA gain = 12 dB, PGA gain = 0 dB12dB
PGA gain resolution3dB
PGA gain rangeMaximum PGA gain – minimum PGA gain30dB
Differential input voltage range for AUX channel2VPP
ANTIALIAS FILTER (Third-Order Elliptic)
fC3-dB filter corner frequencyFILTER_BW = 0 (default)8MHz
FILTER_BW = 17
FILTER_BW = 210.5
FILTER_BW = 312
3-dB filter corner frequency toleranceFor all FILTER_BW settings±5%
ATT2FCFilter attenuationAt 2 × fC30dBc
ATTSTPBNDStop-band attenuation (fIN > 2.25 × fC)40
RPPSBNDRipple in pass band1.5dB
POWER
Total core power, per channelIdle channel, excluding DRVDD power64mW
IAVDD18AVDD18 current consumptionDefault mode131145mA
With HIGH_POW_LNA mode enabled153
With HPL_EN mode enabled135
IAVDD3AVDD3 current consumption1.53.5mA
IDVDD18DVDD18 current consumption812mA
IDRVDDDRVDD current consumption5-pF load, toggle data test pattern modeDRVDD = 3.3 V14mA
DRVDD = 1.8 V8.5
15-pF load, toggle data test pattern modeDRVDD = 3.3 V36
DRVDD = 1.8 V20
Power-down5mW
STBY power15mW