SBASB81 December   2024 AFE5401-EP

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Pin Configuration and Functions
    1.     Pin Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Electrical Characteristics
    6. 5.6  Digital Characteristics
    7. 5.7  Timing Requirements: Output Interface
    8. 5.8  Timing Requirements: RESET
    9. 5.9  Timing Requirements: Serial Interface Operation
    10. 5.10 Typical Characteristics
  7. 6 Parameter Measurement Information
    1. 6.1 Timing Requirements: Across Output Serialization Modes
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Low-Noise Amplifier (LNA)
      2. 7.3.2 Programmable Gain Amplifier (PGA)
      3. 7.3.3 Antialiasing Filter
      4. 7.3.4 Analog-to-Digital Converter (ADC)
      5. 7.3.5 Digital Gain
      6. 7.3.6 Input Clock Divider
      7. 7.3.7 Data Output Serialization
      8. 7.3.8 Setting the Input Common-Mode Voltage for the Analog Inputs
        1. 7.3.8.1 Main Channels
        2. 7.3.8.2 Auxiliary Channel
    4. 7.4 Device Functional Modes
      1. 7.4.1 Equalizer Mode
      2. 7.4.2 Data Output Mode
        1. 7.4.2.1 Header
        2. 7.4.2.2 Test Pattern Mode
      3. 7.4.3 Parity
      4. 7.4.4 Standby, Power-Down Mode
      5. 7.4.5 Digital Filtering to Improve Stop-Band Attenuation
        1. 7.4.5.1 Decimate-by-2 Mode
        2. 7.4.5.2 Decimate-by-4 Mode
      6. 7.4.6 Diagnostic Mode
      7. 7.4.7 Signal Chain Probe
    5. 7.5 Programming
      1. 7.5.1 Serial Interface
      2. 7.5.2 Register Initialization
        1. 7.5.2.1 Register Write Mode
        2. 7.5.2.2 Register Read Mode
      3. 7.5.3 CMOS Output Interface
        1. 7.5.3.1 Synchronization and Triggering
    6. 7.6 Register Maps
      1. 7.6.1 Functional Register Map
      2. 7.6.2 Register Descriptions
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Power Supply Recommendations
      1. 8.3.1 Power Supply Sequencing
      2. 8.3.2 Power Supply Decoupling
    4. 8.4 Layout
      1. 8.4.1 Layout Guidelines
      2. 8.4.2 Layout Example
  10. 9 Revision History
  11. 10Device and Documentation Support
    1. 10.1 Documentation Support
      1. 10.1.1 Related Documentation
    2. 10.2 Receiving Notification of Documentation Updates
    3. 10.3 Community Resources
    4. 10.4 Trademarks
  12. 11Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.4.6 Diagnostic Mode

The device offers various diagnostic modes to check proper device operation at a system level. These modes can be enabled using the SPI and the outputs of these modes are stored in diagnostic read-only registers.

  1. Internal reference status check: In this mode, the on-chip band-gap voltage, ADC reference, and clock generation are verified for functionality. Reading a 0 on these bits indicates that these blocks are functioning properly. The DIAG_MODE_EN register bit must be set to 1. The DIG_REG register bits for this mode are:
    • DIG_REG[0] for ADC references,
    • DIG_REG[1] for band gap, and
    • DIG_REG[2] for clock generation.
  2. DC input force: In this mode, a dc voltage can be internally forced at the LNA input to test the entire signal chain. During this test, the device analog inputs should be left floating. This mode can be asserted by setting the DC_INP_EN bit to 1 and programming the DC_INP_PROG[0:2] bits. In this mode, the equalizer is disabled internally.
  3. Variance (noise) and mean measurement: Variance and mean of the ADC output can be analyzed using the on-chip STAT module. The STAT_EN, STAT_CALC_CYCLE, and STAT_CH_SEL, STAT_CH_AUTO_SEL options should be set to compute the variance and mean. These values can be monitored using channel-specific, read-only registers. Alternatively, these values can also be read using HEADER_MODE. Output variance and mean calculation is determined by Equation 3.
    Equation 3. AFE5401-EP

    STAT_CALC_CYCLE must be set to a large value to obtain better accuracy. Mean provides the average dc value of the ADC output (mid code). The STAT module integration time is defined by: tAFE_CLK × 2(STAT_CALC_CYCLE+1) when the STAT_CH_SEL option is selected. When STAT_CH_AUTO_SEL is enabled, the STAT module integration time is defined by: 4 × tAFE_CLK × 2(STAT_CALC_CYCLE+1).

  4. Temperature sensor: The device junction temperature measurement can be enabled and monitored using TEMP_SENS_EN and TEMP_CONV_EN. The temperature output is saved in a diagnostic read-only register, TEMP_DATA. Alternatively, this data can also be read using HEADER_MODE. The TEMP_DATA value is a 9-bit, twos complement data in degrees Celsius. The temperature data is internally updated as per Equation 4:
    Equation 4. Temperature Data Update Cycle = 1024 × TAFE_CLK × 16