Typical values at TA = +25°C with
nominal supplies. Default conditions: TX input data rate = 491.52 MSPS,
fDAC = 11796.48 MSPS (24x interpolation), interleave mode,
1st Nyquist zone output, PLL clock mode with fREF = 491.52
MHz, AOUT = –1 dBFS, DSA = 0 dB, Sin(x)/x enabled, DSA calibrated, TX
Clock Dither Enabled
| Aout = -0.5 dFBS, 3.5 GHz Matching,
included PCB and cable losses |
|
|
Figure 7-118 TX
Output Power vs Frequency
| 3.5
GHz Matching, included PCB and cable losses |
| Differential Gain Error = POUT(DSA Setting –
1) – POUT(DSA Setting) + 1 |
Figure 7-120 TX
Uncalibrated Differential Gain Error vs DSA Setting and Channel at 3.5
GHz
| 3.5
GHz Matching, included PCB and cable losses |
| Integrated Gain Error = POUT(DSA Setting) –
POUT(DSA Setting = 0) + (DSA
Setting) |
Figure 7-122 TX
Uncalibrated Integrated Gain Error vs DSA Setting and Channel at 3.5
GHz
| 3.5
GHz Matching, included PCB and cable losses |
|
|
Figure 7-124 TX
Uncalibrated Differential Phase Error vs DSA Setting and Channel at 3.5
GHz
| 3.5
GHz Matching, included PCB and cable losses |
Figure 7-126 TX
Uncalibrated Integrated Phase Error vs DSA Setting and Channel at 3.5
GHz
Figure 7-128 TX
Uncalibrated Differential Gain Error vs DSA Setting and Temperature at 3.5
GHz
Figure 7-130 TX
Uncalibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5
GHz
| 3.5
GHz Matching, 1TX |
| Differential Phase Error = PhaseOUT(DSA
Setting – 1) – PhaseOUT(DSA Setting) |
Figure 7-132 TX
Uncalibrated Differential Phase Error vs DSA setting and Temperature at 3.5
GHz
| 3.5
GHz Matching, 1TX |
| Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting=0) |
Figure 7-134 TX
Uncalibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5
GHz
A.
| fDAC=11796.48MSPS, interleave mode,
matching at 3.5GHz, Aout = –13 dBFS. |
|
Figure 7-136 TX
NSD vs DSA Setting at 3.5 GHz
| 20-MHz
tone spacing, 3.5 GHz Matching |
|
Figure 7-138 TX
IMD3 vs Digital Amplitude and Channel at 3.5 GHz
| 3.5
GHz Matching, single carrier 20-MHz BW TM1.1 LTE |
Figure 7-140 TX
20-MHz LTE ACPR vs DSA Setting at 3.5 GHz
| 3.5
GHz Matching, single carrier 20-MHz BW TM1.1 LTE |
Figure 7-142 TX
20-MHz LTE ACPR vs Digital Level at 3.5 GHz
| Matching at 3.5 GHz, fDAC = 11.79648GSPS,
interleave mode, normalized to output power at harmonic
frequency |
Figure 7-144 TX
Single Tone HD2 vs Frequency and Digital Level at 3.5 GHz
| Matching at 3.5 GHz, fDAC = 11.79648GSPS,
interleave mode. |
|
Figure 7-146 TX
Single Tone (–1 dBFS) Output Spectrum at 3.5 GHz (0 -
fDAC)
| Matching at 3.5 GHz, fDAC = 11.79648GSPS,
interleave mode. |
Figure 7-148 TX
Single Tone (–12 dBFS) Output Spectrum at 3.5 GHz
(0-fDAC)
| Aout = -0.5 dFBS, 3.5 GHz Matching,
included PCB and cable losses |
|
Figure 7-119 TX
Output Power vs DSA Setting at 3.5 GHz
| 3.5
GHz Matching, included PCB and cable losses |
| Differential Gain Error = POUT(DSA Setting –
1) – POUT(DSA Setting) + 1 |
Figure 7-121 TX
Calibrated Differential Gain Error vs DSA Setting and Channel at 3.5
GHz
| 3.5
GHz Matching, included PCB and cable losses |
| Integrated Gain Error = POUT(DSA Setting) –
POUT(DSA Setting = 0) + (DSA
Setting) |
Figure 7-123 TX
Calibrated Integrated Gain Error vs DSA Setting and Channel at 3.5
GHz
| 3.5
GHz Matching, included PCB and cable losses |
| Phase
DNL spike may occur at any DSA setting. |
Figure 7-125 TX
Calibrated Differential Phase Error vs DSA Setting and Channel at 3.5
GHz
| 3.5
GHz Matching, included PCB and cable losses |
Figure 7-127 TX
Calibrated Integrated Phase Error vs DSA Setting and Channel at 3.5
GHz
| 3.5
GHz Matching, 1TX, Calibrated at 25°C |
Figure 7-129 TX
Calibrated Differential Gain Error vs DSA Setting and Temperature at 3.5
GHz
| 3.5
GHz Matching, 1TX, Calibrated at 25°C |
|
Figure 7-131 TX
Calibrated Integrated Gain Error vs DSA Setting and Temperature at 3.5
GHz
| 3.5
GHz Matching, 1TX, Calibrated at 25°C |
| Differential Phase Error = PhaseOUT(DSA
Setting – 1) – PhaseOUT(DSA Setting) |
Figure 7-133 TX
Calibrated Differential Phase Error vs DSA Setting and Temperature at 3.5
GHz
| 3.5
GHz Matching, 1TX, Calibrated at 25°C |
| Integrated Phase Error = Phase(DSA Setting) – Phase(DSA
Setting = 0) |
Figure 7-135 TX
Calibrated Integrated Phase Error vs DSA Setting and Temperature at 3.5
GHz
| 20-MHz
tone spacing, 3.5 GHz Matching, –13 dBFS each tone,
included PCB and cable losses |
|
Figure 7-137 TX
IMD3 vs DSA Setting at 3.5 GHz
| 3.5
GHz Matching, single carrier 20-MHz BW TM1.1 LTE |
Figure 7-139 TX
20-MHz LTE Output Spectrum at 3.5 GHz (Band 42)
| 3.5
GHz Matching, single carrier 20-MHz BW TM1.1 LTE |
Figure 7-141 TX
20-MHz LTE alt-ACPR vs DSA Setting at 3.5 GHz
| 3.5
GHz Matching, single carrier 20-MHz BW TM1.1 LTE |
Figure 7-143 TX
20-MHz LTE alt-ACPR vs Digital Level at 3.5 GHz
| Matching at 3.5 GHz, fDAC = 11.79648GSPS,
interleave mode, normalized to output power at harmonic
frequency. Dip is due to HD3 falling near DC. |
Figure 7-145 TX
Single Tone HD3 vs Frequency and Digital Level at 3.5 GHz
| Matching at 3.5 GHz, fDAC = 11.79648GSPS,
interleave mode. |
Figure 7-147 TX
Single Tone (–6 dBFS) Output Spectrum at 3.5 GHz (0-fDAC)