SPRSPA3A March 2024 – September 2024 AM67 , AM67A
PRODUCTION DATA
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Table 6-107, Figure 6-79, Table 6-108, and Figure 6-80 present timing requirements and switching characteristics for MMC0 – UHS-I SDR25 Mode.
NO. | MIN | MAX | UNIT | ||
---|---|---|---|---|---|
SDR251 | tsu(cmdV-clkH) | Setup time, MMC0_CMD valid before MMC0_CLK rising edge | 2.15 | ns | |
SDR252 | th(clkH-cmdV) | Hold time, MMC0_CMD valid after MMC0_CLK rising edge | 1.27 | ns | |
SDR253 | tsu(dV-clkH) | Setup time, MMC0_DAT[3:0] valid before MMC0_CLK rising edge | 2.15 | ns | |
SDR254 | th(clkH-dV) | Hold time, MMC0_DAT[3:0] valid after MMC0_CLK rising edge | 1.27 | ns |
NO. | PARAMETER | MIN | MAX | UNIT | |
---|---|---|---|---|---|
fop(clk) | Operating frequency, MMC0_CLK | 50 | MHz | ||
SDR255 | tc(clk) | Cycle time, MMC0_CLK | 20 | ns | |
SDR256 | tw(clkH) | Pulse duration, MMC0_CLK high | 9.2 | ns | |
SDR257 | tw(clkL) | Pulse duration, MMC0_CLK low | 9.2 | ns | |
SDR258 | td(clkL-cmdV) | Delay time, MMC0_CLK rising edge to MMC0_CMD transition | 2.4 | 8.1 | ns |
SDR259 | td(clkL-dV) | Delay time, MMC0_CLK rising edge to MMC0_DAT[3:0] transition | 2.4 | 8.1 | ns |