JAJS323D February   2008  – June 2024 AMC1203

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagram
    12. 5.12 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Digital Output
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Shunt Resistor Sizing
        2. 7.2.2.2 Input Filter Design
        3. 7.2.2.3 Bitstream Filtering
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.10 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fCLK Internal clock frequency 8 10 12 MHz
tCLK CLKOUT clock period 83.3 100 125 ns
tHIGH CLKOUT high time (tCLK / 2) – 8(1) tCLK / 2 (tCLK / 2) + 8(1) ns
tD DOUT delay time after falling edge of CLKOUT –2 2 ns
tS DOUT setup time prior to rising edge of CLKOUT 31.5 ns
tH DOUT hold time after rising edge of CLKOUT 31.5 ns
(1) tCLK refers to the actual clock period of the device