JAJS323D February   2008  – June 2024 AMC1203

PRODUCTION DATA  

  1.   1
  2. 1 特長
  3. 2 アプリケーション
  4. 3 概要
  5.   Device Comparison Table
  6. 4 Pin Configuration and Functions
  7. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Thermal Information
    5. 5.5  Power Ratings
    6. 5.6  Insulation Specifications
    7. 5.7  Safety-Related Certifications
    8. 5.8  Safety Limiting Values
    9. 5.9  Electrical Characteristics
    10. 5.10 Switching Characteristics
    11. 5.11 Timing Diagram
    12. 5.12 Typical Characteristics
  8. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Analog Input
      2. 6.3.2 Modulator
      3. 6.3.3 Digital Output
    4. 6.4 Device Functional Modes
  9. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
        1. 7.2.2.1 Shunt Resistor Sizing
        2. 7.2.2.2 Input Filter Design
        3. 7.2.2.3 Bitstream Filtering
      3. 7.2.3 Application Curve
    3. 7.3 Best Design Practices
    4. 7.4 Power Supply Recommendations
    5. 7.5 Layout
      1. 7.5.1 Layout Guidelines
      2. 7.5.2 Layout Example
  10. 8 Device and Documentation Support
    1. 8.1 Documentation Support
      1. 8.1.1 Related Documentation
    2. 8.2 ドキュメントの更新通知を受け取る方法
    3. 8.3 サポート・リソース
    4. 8.4 Trademarks
    5. 8.5 静電気放電に関する注意事項
    6. 8.6 用語集
  11. 9 Revision History
  12. 10Mechanical, Packaging, and Orderable Information
    1. 10.1 Mechanical Data

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

5.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air (DUB package) ≥ 7 mm
Shortest pin-to-pin distance through air (PSA package) ≥ 6.3
Shortest pin-to-pin distance through air (DW package) ≥ 8
CPG External creepage(1) Shortest pin-to-pin distance across the package surface (DUB) ≥ 7 mm
Shortest pin-to-pin distance across the package surface (PSA) ≥ 6.3
Shortest pin-to-pin distance across the package surface (DW) ≥ 8
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 8 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 175 V
Material group According to IEC 60664-1 IIIa
Overvoltage category
per IEC 60664-1		 Rated mains voltage ≤ 150VRMS I-IV
Rated mains voltage ≤ 300VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)(2)
VIORM Maximum repetitive peak isolation voltage At AC voltage 560 VPK
VIOWM Maximum-rated isolation
working voltage		 At AC voltage (sine wave) 400 VRMS
At DC voltage 560 VDC
VIOTM Maximum transient
isolation voltage		 VTEST = VIOTM, t = 60s (qualification test),
VTEST = 1.2 × VIOTM, t = 1s (100% production test)		 3800 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50µs waveform per IEC 62368-1 3100 VPK
VIOSM Maximum surge
isolation voltage(4)		 Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1		 4000 VPK
qpd Apparent charge(5) Method a, after input/output safety test subgroups 2 and 3,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.2 × VIORM, tm = 10s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vpd(ini) = VIOTM, tini = 60s, Vpd(m) = 1.3 × VIORM, tm = 10s		 ≤ 5
Method b1, at preconditioning (type test) and routine test,
Vpd(ini) = VIOTM, tini = 1s, Vpd(m) = 1.5 × VIORM, tm = 1s		 ≤ 5
Method b2, at routine test (100% production)(7),
Vpd(ini) = VIOTM = Vpd(m), tini = tm = 1s		 ≤ 5
CIO Barrier capacitance,
input to output(6)		 VIO = 0.5 VPP at 1MHz ~1.5 pF
RIO Insulation resistance,
input to output(6)		 VIO = 500V at TA = 25°C > 1012 Ω
VIO = 500V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/105/21
UL1577
VISO Withstand isolation voltage VTEST = VISO, t = 60s (qualification test),
VTEST = 1.2 × VISO, t = 1s (100% production test)		 2700 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
(7) Either method b1 or b2 is used in production.