JAJSIJ6F April   2011  – February 2020 AMC1204

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      デバイスのブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Modulator
      3. 8.3.3 Digital Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Filter Usage
    2. 9.2 Typical Application
      1. 9.2.1 Frequency Inverter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Example of a Resolver-Based Motor Control Analog Front End
      3. 9.2.3 Isolated Voltage Sensing
        1. 9.2.3.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.6 Insulation Specifications

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air, DW package ≥ 8 mm
Shortest pin-to-pin distance through air, DWV package ≥ 8.5
CPG External creepage(1) Shortest pin-to-pin distance across the package surface, DW package ≥ 8 mm
Shortest pin-to-pin distance across the package surface, DWV package ≥ 8.5
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 0.014 mm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112, DW package ≥ 400 V
DIN EN 60112 (VDE 0303-11); IEC 60112, DWV package ≥ 175
Material group According to IEC 60664-1, DW package II
According to IEC 60664-1, DWV package III
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 300 VRMS I-IV
Rated mains voltage ≤ 600 VRMS I-III
DIN VDE V 0884-11: 2017-01(2)
VIORM Maximum repetitive peak isolation voltage At ac voltage (bipolar) 1200 VPK
VIOWM Maximum-rated isolation working voltage At ac voltage (sine wave) 849 VRMS
At dc voltage 1200 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification test), AMC1204B 4250 VPK
VTEST = 1.2 × VIOTM, t = 1 s (100% production test), AMC1204B 5100
VTEST = VIOTM, t = 60 s (qualification test), AMC1204 4000
VTEST = 1.2 × VIOTM, t = 1 s (100% production test), AMC1204 4800
VIOSM Maximum surge isolation voltage(3) Test method per IEC 60065, 1.2/50-µs waveform,
VTEST = 1.3 × VIOSM = 6000 VPK (qualification)		 4615 VPK
qpd Apparent charge(4) Method a, after input/output safety test subgroup 2 / 3,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.2 × VIORM = 1440 VPK, tm = 10 s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vini = VIOTM, tini = 60 s,
Vpd(m) = 1.3 × VIORM = 1560 VPK, tm = 10 s		 ≤ 5
Method b1, at routine test (100% production) and preconditioning (type test), Vini = VIOTM, tini = 1 s,
Vpd(m) = 1.5 × VIORM = 1800 VPK, tm = 1 s		 ≤ 5
CIO Barrier capacitance, input to output(5) VIO = 0.5 VPP at 1 MHz 1.2 pF
RIO Insulation resistance, input to output(5) VIO = 500 V at TA < 85°C > 1012 Ω
VIO = 500 V at 85°C < TA < 105°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO = 3005 VRMS or 4250 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 3606 VRMS, t = 1 s (100% production test), AMC1204B 3005 VRMS
VTEST = VISO = 2500 VRMS or 4000 VDC, t = 60 s (qualification), VTEST = 1.2 × VISO = 2800 VRMS, t = 1 s (100% production test), AMC1204 2500
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves and ribs on the PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier are tied together, creating a two-pin device.