JAJSIJ6F April   2011  – February 2020 AMC1204

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      デバイスのブロック図
  4. 4 改訂履歴
  5. 5 概要（続き）
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics
    10. 7.10 Timing Requirements
    11. 7.11 Insulation Characteristics Curves
    12. 7.12 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Modulator
      3. 8.3.3 Digital Output
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Filter Usage
    2. 9.2 Typical Application
      1. 9.2.1 Frequency Inverter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
      2. 9.2.2 Example of a Resolver-Based Motor Control Analog Front End
      3. 9.2.3 Isolated Voltage Sensing
        1. 9.2.3.1 Design Requirements
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 ドキュメントのサポート
      1. 12.1.1 関連資料
    2. 12.2 ドキュメントの更新通知を受け取る方法
    3. 12.3 サポート・リソース
    4. 12.4 商標
    5. 12.5 静電気放電に関する注意事項
    6. 12.6 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics

All minimum/maximum specifications at TA = –40°C to 105°C, AVDD = 4.5 V to 5.5 V, DVDD = 2.7 V to 5.5 V, VINP = –250 mV to 250 mV, VINN = 0 V, and sinc3 filter with OSR = 256, unless otherwise noted.
Typical values are at TA = 25°C, AVDD = 5 V, and DVDD = 3.3 V.
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
RESOLUTION
Resolution 16 Bits
DC ACCURACY
INL Integral linearity error(1) TA = –40°C to 85°C –8 ±2 8 LSB
TA = –40°C to 105°C –16 ±5 16 LSB
DNL Differential nonlinearity –1 1 LSB
VOS Offset error(2) –1 ±0.1 1 mV
TCVOS Offset error thermal drift –3.5 ±1 3.5 μV/°C
GERR Gain error(2) –2% ±0.5% 2%
TCGERR Gain error thermal drift ±30 ppm/°C
PSRR Power-supply rejection ratio 79 dB
ANALOG INPUTS
FSR Full-scale differential voltage input range VINP – VINN ±320 mV
Specified FSR –250 250 mV
VCM Operating common-mode signal(3) –160 AVDD mV
CI Input capacitance to AGND VINP or VINN 7 pF
CID Differential input capacitance 3.5 pF
RID Differential input resistance 12.5 kΩ
IIL Input leakage current VINP – VINN = ±250 mV –10 10 μA
VINP – VINN = ±320 mV –50 50 μA
CMTI Common-mode transient immunity 15 kV/μs
CMRR Common-mode rejection ratio VIN from 0 V to 5 V at 0 Hz 108 dB
VIN from 0 V to 5 V at 100 kHz 114 dB
EXTERNAL CLOCK
tCLKIN Clock period 45.5 50 200 ns
fCLKIN Input clock frequency 5 20 22 MHz
DutyCLKIN Duty cycle 5 MHz ≤ fCLKIN < 20 MHz 40% 50% 60%
20 MHz ≤ fCLKIN ≤ 22 MHz 45% 50% 55%
AC ACCURACY
SINAD Signal-to-noise + distortion fIN = 1kHz, TA = –40°C to 85°C 78 87 dB
fIN = 1kHz, TA = –40°C to 105°C 70 87 dB
SNR Signal-to-noise ratio fIN = 1kHz, TA = –40°C to 85°C 84 88 dB
fIN = 1kHz, TA = –40°C to 105°C 83 88 dB
THD Total harmonic distortion fIN = 1kHz, TA = –40°C to 85°C –96 –80 dB
fIN = 1kHz, TA = –40°C to 105°C –96 –70 dB
SFDR Spurious-free dynamic range fIN = 1kHz, TA = –40°C to 85°C 82 96 dB
fIN = 1kHz, TA = –40°C to 105°C 72 96 dB
DIGITAL INPUTS(3)
IIN Input current VIN = DVDD to DGND –10 10 μA
CIN Input capacitance 5 pF
CMOS Logic Family (CMOS With Schmitt-Trigger)
VIH High-level input voltage DVDD = 4.5V to 5.5V 0.7DVDD DVDD + 0.3 V
VIL Low-level input voltage DVDD = 4.5V to 5.5V –0.3 0.3DVDD V
LVCMOS Logic Family
VIH High-level input voltage DVDD = 2.7 V to 3.6 V 2 DVDD + 0.3 V
VIL Low-level input voltage DVDD = 2.7 V to 3.6 V –0.3 0.8 V
DIGITAL OUTPUTS(3)
COUT Output capacitance 5 pF
CLOAD Load capacitance 30 pF
CMOS Logic Family
VOH High-level output voltage DVDD = 4.5 V, IOH = –100 µA 4.4 V
VOL Low-level output voltage DVDD = 4.5 V, IOL = 100 µA 0.5 V
LVCMOS Logic Family
VOH High-level output voltage IOH = 20 µA DVDD – 0.1 V
IOH = –4 mA,
2.7 V ≤ DVDD ≤ 3.6 V		 DVDD – 0.4 V
IOH = –4 mA,
4.5 V ≤ DVDD ≤ 5.5 V		 DVDD – 0.8 V
VOL Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4 V
POWER SUPPLY
AVDD High-side supply voltage 4.5 5 5.5 V
DVDD Controller-side supply voltage 2.7 3.3 5.5 V
IAVDD High-side supply current 4.5 V ≤ AVDD ≤ 5.5 V 11 16 mA
IDVDD Controller-side supply current 2.7 V ≤ DVDD ≤ 3.6 V 2 4 mA
4.5V ≤ DVDD ≤ 5.5 V 2.8 5 mA
PD Power dissipation AVDD = 5.5 V, DVDD = 3.6 V 61.6 102.4 mW
(1) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as number of LSBs or as a percent of the specified 500-mV input range.
(2) Maximum values, including temperature drift, are ensured over the full specified temperature range.
(3) Ensured by design.