JAJSEL8C June   2018  – November 2022 AMC1211-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications 
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Timing Diagram
    12. 6.12 Insulation Characteristics Curves
    13. 6.13 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Isolation Channel Signal Transmission
      3. 7.3.3 Analog Output
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Input Filter Design
        2. 8.2.2.2 Differential to Single-Ended Output Conversion
      3. 8.2.3 Application Curve
    3. 8.3 Best Design Practices
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  9. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 サポート・リソース
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  10. 10Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

6.6 Insulation Specifications 

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS VALUE UNIT
GENERAL
CLR External clearance(1) Shortest pin-to-pin distance through air ≥ 8.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface ≥ 8.5 mm
DTI Distance through insulation Minimum internal gap (internal clearance) of the insulation ≥ 21 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 ≥ 600 V
Material group According to IEC 60664-1 I
Overvoltage category
per IEC 60664-1		 Rated mains voltage ≤ 150 VRMS I-IV
Rated mains voltage ≤ 300 VRMS I-III
DIN EN IEC 60747-17 (VDE 0884-17)2
VIORM Maximum repetitive peak isolation voltage At AC voltage 1400 VPK
VIOWM Maximum-rated isolation
working voltage		 At AC voltage (sine wave) 1000 VRMS
At DC voltage 1400 VDC
VIOTM Maximum transient
isolation voltage		 VTEST = VIOTM, t = 60 s (qualification test),
VTEST = 1.2 × VIOTM, t = 1 s (100% production test)		 4250 VPK
VIMP Maximum impulse voltage(3) Tested in air, 1.2/50-µs waveform per IEC 62368-1 6000 VPK
VIOSM Maximum surge
isolation voltage(4)		 Tested in oil (qualification test),
1.2/50-µs waveform per IEC 62368-1 		7800 VPK
qpd Apparent charge(5) Method a, after input/output safety test subgroups 2 and 3,
Vpd(ini) = VIOTM, tini = 60 s, Vpd(m) = 1.2 × VIORM, tm = 10 s		 ≤ 5 pC
Method a, after environmental tests subgroup 1,
Vpd(ini) = VIOTM, tini = 60 s, Vpd(m) = 1.3 × VIORM, tm = 10 s		 ≤ 5
Method b1, at preconditioning (type test) and routine test,
Vpd(ini) = VIOTM, tini = 1 s, Vpd(m) = 1.5 × VIORM, tm = 1 s		 ≤ 5
Method b2, at routine test (100% production)(7),
Vpd(ini) = VIOTM = Vpd(m); tini = tm = 1 s		 ≤ 5
CIO Barrier capacitance,
input to output(6)		 VIO = 0.5 VPP at 1 MHz ~1.5 pF
RIO Insulation resistance,
input to output(6)		 VIO = 500 V at TA = 25°C > 1012 Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS = 150°C > 109
Pollution degree 2
Climatic category 55/125/21
UL1577
VISO Withstand isolation voltage VTEST = VISO, t = 60 s (qualification test),
VTEST = 1.2 × VISO, t = 1 s (100% production test)		 3000 VRMS
(1) Apply creepage and clearance requirements according to the specific equipment isolation standards of an application. Care must be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed circuit board (PCB) do not reduce this distance. Creepage and clearance on a PCB become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a PCB are used to help increase these specifications.
(2) This coupler is suitable for safe electrical insulation only within the safety ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air to determine the surge immunity of the package.
(4) Testing is carried out in oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier are tied together, creating a two-pin device.
(7) Either method b1 or b2 is used in production.