SBAS655F September 2014 – January 2020 AMC1304L05 , AMC1304L25 , AMC1304M05 , AMC1304M25
PRODUCTION DATA.
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
ANALOG INPUTS | ||||||
VClipping | Maximum differential voltage input range
(AINP-AINN) |
±62.5 | mV | |||
FSR | Specified linear full-scale range
(AINP-AINN) |
–50 | 50 | mV | ||
VCM | Operating common-mode input range | –0.032 | 1.2 | V | ||
CID | Differential input capacitance | 2 | pF | |||
IIB | Input bias current | Inputs shorted to AGND | –97 | –72 | –57 | μA |
RID | Differential input resistance | 5 | kΩ | |||
IIO | Input offset current | ±5 | nA | |||
CMTI | Common-mode transient immunity | 15 | kV/μs | |||
CMRR | Common-mode rejection ratio | fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max |
–98 | dB | ||
fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max |
–85 | |||||
BW | Input bandwidth | 800 | kHz | |||
DC ACCURACY | ||||||
DNL | Differential nonlinearity | Resolution: 16 bits | –0.99 | 0.99 | LSB | |
INL | Integral nonlinearity (1) | Resolution: 16 bits | –4 | ±1.5 | 4 | LSB |
EO | Offset error | Initial, at 25°C | –50 | ±2.5 | 50 | µV |
TCEO | Offset error thermal drift (2) | –1.3 | 1.3 | μV/°C | ||
EG | Gain error | Initial, at 25°C | –0.3% | –0.02% | 0.3% | |
TCEG | Gain error thermal drift (3) | –40 | ±20 | 40 | ppm/°C | |
PSRR | Power-supply rejection ratio | LDOIN from 4 V to 18 V, at dc | –110 | dB | ||
LDOIN from 4 V to 18 V, from 0.1 Hz to 50 kHz | –110 | |||||
AC ACCURACY | ||||||
SNR | Signal-to-noise ratio | fIN = 1 kHz | 76 | 81.5 | dB | |
SINAD | Signal-to-noise + distortion | fIN = 1 kHz | 76 | 81 | dB | |
THD | Total harmonic distortion | fIN = 1 kHz | –90 | –81 | dB | |
SFDR | Spurious-free dynamic range | fIN = 1 kHz | 81 | 90 | dB | |
DIGITAL INPUTS/OUTPUTS | ||||||
External Clock | ||||||
fCLKIN | Input clock frequency | 5 | 20 | 20.1 | MHz | |
DutyCLKIN | Duty cycle | 5 MHz ≤ fCLKIN ≤ 20.1 MHz | 40% | 50% | 60% | |
CMOS Logic Family (AMC1304M05, CMOS with Schmitt Trigger) | ||||||
IIN | Input current | DGND ≤ VIN ≤ DVDD | –1 | 1 | μA | |
CIN | Input capacitance | 5 | pF | |||
VIH | High-level input voltage | 0.7 × DVDD | DVDD + 0.3 | V | ||
VIL | Low-level input voltage | –0.3 | 0.3 × DVDD | V | ||
CLOAD | Output load capacitance | fCLKIN = 20 MHz | 30 | pF | ||
VOH | High-level output voltage | IOH = –20 µA | DVDD – 0.1 | V | ||
IOH = –4 mA | DVDD – 0.4 | |||||
VOL | Low-level output voltage | IOL = 20 µA | 0.1 | V | ||
IOL = 4 mA | 0.4 | |||||
LVDS Logic Family (AMC1304L05)(4) | ||||||
VT | Differential output voltage | RLOAD = 100 Ω | 250 | 350 | 450 | mV |
VOC | Common-mode output voltage | 1.125 | 1.23 | 1.375 | V | |
VID | Differential input voltage | 100 | 350 | 600 | mV | |
VIC | Common-mode input voltage | VID = 100 mV | 0.05 | 1.25 | 3.25 | V |
II | Receiver input current | DGND ≤ VIN ≤ 3.3 V | –24 | 0 | 20 | µA |
POWER SUPPLY | ||||||
LDOIN | LDOIN pin input voltage | 4.0 | 15.0 | 18.0 | V | |
VCAP | VCAP pin voltage | 3.45 | V | |||
ILDOIN | LDOIN pin input current | 5.3 | 6.5 | mA | ||
DVDD | Controller-side supply voltage | 3.0 | 3.3 | 5.5 | V | |
IDVDD | Controller-side supply current | LVDS, RLOAD = 100 Ω | 6.1 | 8 | mA | |
CMOS, 3.0 V ≤ DVDD ≤ 3.6 V,
CLOAD = 5 pF |
2.7 | 4.0 | ||||
CMOS, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 5 pF |
3.2 | 5.5 |