JAJSNI7 February   2022 AMC1306M05-Q1

PRODUCTION DATA  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8.     Safety Limiting Values
    9. 6.8  Electrical Characteristics
    10.     Switching Characteristics
    11. 6.9  Timing Diagrams
    12. 6.10 Insulation Characteristics Curves
    13. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Analog Input
      2. 7.3.2 Modulator
      3. 7.3.3 Isolation Channel Signal Transmission
      4. 7.3.4 Digital Output
        1. 7.3.4.1 Output Behavior in Case of a Full-Scale Input
        2. 7.3.4.2 Output Behavior in Case of Input Common-Mode Overrange
        3. 7.3.4.3 Output Behavior in Case of a Missing High-Side Supply
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
        1. 8.2.2.1 Shunt Resistor Sizing
        2. 8.2.2.2 Input Filter Design
        3. 8.2.2.3 Bitstream Filtering
      3. 8.2.3 Application Curve
    3. 8.3 What to Do and What Not to Do
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 Receiving Notification of Documentation Updates
    3. 11.3 サポート・リソース
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

パッケージ・オプション

メカニカル・データ（パッケージ｜ピン）
サーマルパッド・メカニカル・データ
発注情報

8.2.2.3 Bitstream Filtering

The modulator generates a bitstream that is processed by a digital filter to obtain a digital word similar to a conversion result of a conventional analog-to-digital converter (ADC). As described by Equation 2, a very simple filter built with minimal effort and hardware, is a sinc3-type filter:

Equation 2. H z = 1 - z - O S R 1 - z - 1 3

This filter provides the best output performance at the lowest hardware size (count of digital gates) for a second-order modulator. All characterization in this document is also done with a sinc3 filter with an oversampling ratio (OSR) of 256 and an output word width of 16 bits, unless specified otherwise. The measured effective number of bits (ENOB) as a function of the OSR is illustrated in Figure 8-3 of the Section 8.2 section.

A Delta Sigma Modulator Filter Calculator is available for download at www.ti.com that aids in the filter design and selecting the right OSR and filter order to achieve the desired output resolution and filter response time.

An example code for implementing a sinc3 filter in an FPGA is discussed in the Combining the ADS1202 with an FPGA Digital Filter for Current Measurement in Motor Control Applications application note, available for download at www.ti.com.

For modulator output bitstream filtering, a device from TI's C2000™ or Sitara™ microcontroller families is recommended. These families support up to eight channels of dedicated hardwired filter structures that significantly simplify system level design by offering two filtering paths per channel: one providing high-accuracy results for the control loop and one fast-response path for overcurrent detection.

A delta sigma modulator filter calculator is available for download at www.ti.com that aids in the filter design and selecting the right OSR and filter order to achieve the desired output resolution and filter response time.