JAJSCZ5C March   2017  – Janaury 2020 AMC1306E05 , AMC1306E25 , AMC1306M05 , AMC1306M25

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: AMC1306x05
    10. 7.10 Electrical Characteristics: AMC1306x25
    11. 7.11 Switching Characteristics
    12. 7.12 Insulation Characteristics Curves
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Modulator
      3. 8.3.3 Isolation Channel Signal Transmission
      4. 8.3.4 Digital Output
      5. 8.3.5 Manchester Coding Feature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Output
      2. 8.4.2 Output Behavior in Case of a Full-Scale Input
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Filter Usage
    2. 9.2 Typical Applications
      1. 9.2.1 Frequency Inverter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Isolated Voltage Sensing
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
        1. 12.1.1.1 絶縁の用語集
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DWV|8
サーマルパッド・メカニカル・データ
発注情報

7.9 Electrical Characteristics: AMC1306x05

minimum and maximum specifications apply from TA = –40°C to +125°C, AVDD = 3.0 V to 5.5 V, DVDD = 2.7 V to 5.5 V, AINP = –50 mV to 50 mV, AINN = AGND, and sinc3 filter with OSR = 256 (unless otherwise noted); typical specifications are at TA = 25°C, CLKIN = 20 MHz, AVDD = 5 V, and DVDD = 3.3 V
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ANALOG INPUTS
VClipping Differential input voltage before clipping output VIN = AINP – AINN ±64 mV
FSR Specified linear differential full-scale VIN = AINP – AINN –50 50 mV
Absolute common-mode input voltage(1) (AINP + AINN) / 2 to AGND –2 AVDD V
VCM Operating common-mode input voltage (AINP + AINN) / 2 to AGND –0.032 AVDD – 2.1 V
VCMov Common-mode overvoltage detection level(2) (AINP + AINN) / 2 to AGND AVDD - 2 V
CIN Single-ended input capacitance AINN = AGND 4 pF
CIND Differential input capacitance 2 pF
IIB Input bias current AINP = AINN = AGND, IIB = IIBP + IIBN –97 –72 –57 μA
RIN Single-ended input resistance AINN = AGND 4.75 kΩ
RIND Differential input resistance 4.9 kΩ
IIO Input offset current ±10 nA
CMTI Common-mode transient immunity 50 100 kV/μs
CMRR Common-mode rejection ratio AINP = AINN, fIN = 0 Hz,
VCM min ≤ VIN ≤ VCM max 		–99 dB
AINP = AINN, fIN from 0.1 Hz to 50 kHz,
VCM min ≤ VIN ≤ VCM max 		–98
BW Input bandwidth(3) 800 kHz
DC ACCURACY
DNL Differential nonlinearity Resolution: 16 bits –0.99 0.99 LSB
INL Integral nonlinearity(4) Resolution: 16 bits, 4.5 V ≤ AVDD ≤ 5.5 V –4 ±1 4 LSB
Resolution: 16 bits, 3.0 V ≤ AVDD ≤ 3.6 V –5 ±1.5 5
EO Offset error Initial, at 25°C, AINP = AINN = AGND –50 ±2.5 50 µV
TCEO Offset error thermal drift(5) –1 ±0.25 1 μV/°C
EG Gain error Initial, at 25°C –0.2% ±0.005% 0.2%
TCEG Gain error thermal drift(6) –40 ±20 40 ppm/°C
PSRR Power-supply rejection ratio AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V, at dc		 –108 dB
AINP = AINN = AGND,
3.0 V ≤ AVDD ≤ 5.5 V,
10 kHz, 100-mV ripple		 –107
AC ACCURACY
SNR Signal-to-noise ratio fIN = 1 kHz 78 82.5 dB
SINAD Signal-to-noise + distortion fIN = 1 kHz 77.5 82.3 dB
THD Total harmonic distortion 4.5 V ≤ AVDD ≤ 5.5 V,
5 MHz ≤ fCLKIN ≤ 21 MHz, fIN = 1 kHz		 –98 –84 dB
3.0 V ≤ AVDD ≤ 3.6 V,
5 MHz ≤ fCLKIN ≤ 20 MHz, fIN = 1 kHz		 –93 –83
SFDR Spurious-free dynamic range fIN = 1 kHz 83 100 dB
DIGITAL INPUTS/OUTPUTS
CMOS Logic With Schmitt-Trigger
IIN Input current DGND ≤ VIN ≤ DVDD 0 7 µA
CIN Input capacitance 4 pF
VIH High-level input voltage 0.7 × DVDD DVDD + 0.3 V
VIL Low-level input voltage –0.3 0.3 × DVDD V
CLOAD Output load capacitance 30 pF
VOH High-level output voltage IOH = –20 µA DVDD – 0.1 V
IOH = –4 mA DVDD – 0.4
VOL Low-level output voltage IOL = 20 µA 0.1 V
IOL = 4 mA 0.4
POWER SUPPLY
AVDD High-side supply voltage 3.0 5.0 5.5 V
IAVDD High-side supply current 3.0 V ≤ AVDD ≤ 3.6 V 6.3 8.5 mA
4.5 V ≤ AVDD ≤ 5.5 V 7.2 9.8
DVDD Controller-side supply voltage 2.7 3.3 5.5 V
IDVDD Controller-side supply current AMC1306Ex, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 4.1 5.5 mA
AMC1306Mx, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 3.3 4.8
AMC1306Ex, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 5.0 6.9
AMC1306Mx, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 3.9 6.0
(1) Steady-state voltage supported by the device in case of a system failure. See specified common-mode input voltage VCM for normal operation. Observe analog input voltage range as specified in the Absolute Maximum Ratings table.
(2) The common-mode overvoltage detection level has a typical hysteresis of 90 mV.
(3) This is the –3-dB, second-order roll-off frequency of the integrated differential input amplifier to consider for the antialiasing filter design.
(4) Integral nonlinearity is defined as the maximum deviation from a straight line passing through the end-points of the ideal ADC transfer function expressed as a number of LSBs or as a percent of the specified linear full-scale range (FSR).
(5) Offset error drift is calculated using the box method, as described by the following equation:
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 ec_eodrift_bas654.gif
(6) Gain error drift is calculated using the box method, as described by the following equation:
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 ec_egdrift_bas654.gif