JAJSCZ5C March   2017  – Janaury 2020 AMC1306E05 , AMC1306E25 , AMC1306M05 , AMC1306M25

PRODUCTION DATA.  

  1. 1 特長
  2. 2 アプリケーション
  3. 3 概要
    1.     Device Images
      1.      概略回路図
  4. 4 改訂履歴
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Power Ratings
    6. 7.6  Insulation Specifications
    7. 7.7  Safety-Related Certifications
    8. 7.8  Safety Limiting Values
    9. 7.9  Electrical Characteristics: AMC1306x05
    10. 7.10 Electrical Characteristics: AMC1306x25
    11. 7.11 Switching Characteristics
    12. 7.12 Insulation Characteristics Curves
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
      2. 8.3.2 Modulator
      3. 8.3.3 Isolation Channel Signal Transmission
      4. 8.3.4 Digital Output
      5. 8.3.5 Manchester Coding Feature
    4. 8.4 Device Functional Modes
      1. 8.4.1 Fail-Safe Output
      2. 8.4.2 Output Behavior in Case of a Full-Scale Input
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Digital Filter Usage
    2. 9.2 Typical Applications
      1. 9.2.1 Frequency Inverter Application
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 Isolated Voltage Sensing
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
        3. 9.2.2.3 Application Curve
      3. 9.2.3 What To Do and What Not To Do
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12デバイスおよびドキュメントのサポート
    1. 12.1 デバイス・サポート
      1. 12.1.1 デバイスの項目表記
        1. 12.1.1.1 絶縁の用語集
    2. 12.2 ドキュメントのサポート
      1. 12.2.1 関連資料
    3. 12.3 関連リンク
    4. 12.4 ドキュメントの更新通知を受け取る方法
    5. 12.5 コミュニティ・リソース
    6. 12.6 商標
    7. 12.7 静電気放電に関する注意事項
    8. 12.8 Glossary
  13. 13メカニカル、パッケージ、および注文情報

パッケージ・オプション

デバイスごとのパッケージ図は、PDF版データシートをご参照ください。

メカニカル・データ（パッケージ｜ピン）
  • DWV|8
サーマルパッド・メカニカル・データ
発注情報

7.11 Switching Characteristics

over operating ambient temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
fCLKIN CLKIN clock frequency 4.5 V ≤ AVDD ≤ 5.5 V 5 21 MHz
3.0 V ≤ AVDD ≤ 5.5 V 5 20
tCLKIN CLKIN clock period 4.5 V ≤ AVDD ≤ 5.5 V 47.6 200 ns
3.0 V ≤ AVDD ≤ 5.5 V 50 200
tHIGH CLKIN clock high time 20 25 120 ns
tLOW CLKIN clock low time 20 25 120 ns
tH DOUT hold time after rising edge
of CLKIN		 AMC1306Mx(1),
CLOAD = 15 pF		 3.5 ns
tD Rising edge of CLKIN to DOUT valid delay AMC1306Mx(1), CLOAD = 15 pF 15 ns
tr DOUT rise time 10% to 90%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF		 0.8 3.5 ns
10% to 90%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 1.8 3.9
tf DOUT fall time 90% to 10%, 2.7 V ≤ DVDD ≤ 3.6 V,
CLOAD = 15 pF 		0.8 3.5 ns
90% to 10%, 4.5 V ≤ DVDD ≤ 5.5 V,
CLOAD = 15 pF		 1.8 3.9
tISTART Interface startup time DVDD at 2.7 V (min) to DOUT valid with AVDD ≥ 3.0 V 32 32 CLKIN cycles
tASTART Analog startup time AVDD step to 3.0 V with DVDD ≥ 2.7 V, 0.1% settling 0.5 ms
(1) The output of the Manchester encoded versions of the AMC1306Ex can change with every edge of CLKIN with a typical delay of 6 ns; see the Manchester Coding Feature section for additional details.
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 tim_int_bas734.gifFigure 1. Digital Interface Timing
AMC1306E05 AMC1306E25 AMC1306M05 AMC1306M25 tim_start_bas734.gifFigure 2. Device Startup Timing