The DRDY pin is an active-low output that indicates when new conversion data are ready in conversion mode. Connect the DRDY pin to an input on the host to trigger periodic data retrieval in conversion mode. The period between each DRDY falling edge is the data rate period.

The DRDY_HIZ bit in the MODE register configures the state of the DRDY pin when deasserted. By default the bit is 0b, meaning the pin is actively driven high using a push-pull output stage. When the bit is 1b, DRDY behaves like an open-drain digital output. Use a 10-kΩ pullup resistor to pull the pin high when DRDY is not asserted.

The DRDY_FMT bit in the MODE register determines the format of the DRDY signal. When the bit is 0b, new data are indicated by DRDY changing from high to low and remaining low until either all conversion data are shifted out of the device, or remaining low and going high briefly before the next time DRDY transitions low. When the DRDY_FMT bit is 1b, new data are indicated by a short negative pulse on the DRDY pin. If the host does not read conversion data after the DRDY pulse when DRDY_FMT is 1b, the device skips a conversion result and does not provide another DRDY pulse until the second following instance when data are ready because of how the pulse is generated. See the Collecting Data for the First Time or After a Pause in Data Collection section for more information about the behavior of DRDY when data are not consistently read.